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TODSR — Time-of-Day Seconds Register
31
R
W
RESET:
C.3.4 TOD Fraction Register (TODFR)
The 32-bit time-of-day fraction register holds eight bits of data that represent the
binary fraction of a second. It is clocked by the 32.768-kHz LOW_REFCLK divided by
128 (256 Hz). Reads of this register return the value latched when the TOD seconds
register was previously read. Continuous reads return the same value until the
TODSR is read and new data is latched from the fraction counter. These eight bits are
cleared whenever the TODSR is written but are not affected by either reset pin or the
watchdog reset conditions. The fraction counter is undefined after a POR. Writes to
this register cause all eight bits to be set.
Access this register with 32-bit accesses only.
TODFR — TOD Fraction Register
31
30
29
28
R
TOD FRACTION REGISTER
W
Set to ones
RESET:
Undefined on POR
15
14
13
12
R
0
0
0
W
RESET:
C.3.5 TOD Seconds Alarm Register (TODSAR)
The time-of-day seconds alarm register is a 32-bit read/write register which holds
data (in seconds) to be compared to the TOD seconds register. The comparison is
made every 1/256 of a second if the alarm function is enabled by the AE bit in the
TODCSR. Writes to this register inhibit alarm compares until the TODFAR is written.
For proper alarm operation, the fraction alarm register must be (re)written after a
write to this register. This register is not affected by any of the reset conditions.
Access this register with 32-bit loads and stores only.
MOTOROLA
C-8
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
TOD SECONDS REGISTER
Undefined on POR
Figure C-8 TOD Seconds Register
27
26
25
11
10
9
0
0
0
0
Figure C-9 TOD Fraction Register
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
24
23
22
21
0
0
0
8
7
6
5
0
0
0
0
10001008
1000100C
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
MMC2001
REFERENCE MANUAL
0
16
0
0
0
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