Pwm Control Register; Pwm Control Registers - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

Address
10005024
10005026
10005028
1000502A
1000502C
1000502E
10005030
to
10005FFF
10006000
to
10006FFF
C.6.1 PWM Control Register
The PWM control register (PWMCR) controls the overall operation of the PWM chan-
nel. The status of the channel pin is also accessible.
PWMCR0 — PWM0 Control Register
PWMCR1 — PWM1 Control Register
PWMCR2 — PWM2 Control Register
PWMCR3 — PWM3 Control Register
PWMCR4 — PWM4 Control Register
PWMCR5 — PWM5 Control Register
15 14 13 12
R 0 0 0 0
W
RESET:
DOZE — Doze Mode
When the CPU executes a doze instruction and the system is placed in doze mode,
the DOZE bit affects operation of the PWM channel. If this bit is set, the PWM chan-
nel is disabled in doze mode. PWM channel operation is suspended at the end of the
current period. If IRQ_EN is set, an interrupt request is still generated following the
period compare that causes suspension. This interrupt may selectively cause the
CPU to exit doze mode.
0 = PWM channel is unaffected in doze mode
1 = PWM channel is disabled in doze mode
At reset, this bit is cleared to zero.
MMC2001
REFERENCE MANUAL
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Freescale Semiconductor, Inc.
Table C-10 PWM Address Map (Continued)
Use
PWM4 Width Register (PWMWR4)
PWM4 Counter Register (PWMCTR4)
PWM5 Control Register (PWMCR5)
PWM5 Period Register (PWMPR5)
PWM5 Width Register (PWMWR5)
PWM5 Counter Register (PWMCTR5)
Reserved
Not Used (Access causes transfer error)
11 10 9 8
PWM IRQ
DOZE LOAD DATA
IRQ EN
0 0 0 0
Figure C-24 PWM Control Registers
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Access
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
Not Applicable
7 6 5 4
COUNT
DIR POL MODE
0 0 0
10005000
10005008
10005010
10005018
10005020
10005028
3 2 1 0
CLKSEL
EN
0 0 0 0
MOTOROLA
C-23