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SQA — Sequential Breakpoint A Arm Occurrence
This read-only status bit is set when sequential operation is enabled and a memory
breakpoint A event has occurred to enable memory breakpoint B operation. This bit is
cleared on test logic reset or when debug mode is exited with the GO and EX bits set.
PM — Processor Mode
These status bits indicate the processor operating mode. They allow coordination of
the OnCE controller with the CPU to synchronize the two.
16.7 OnCE Decoder (ODEC)
The OnCE decoder (ODEC) receives as input the 8-bit command from the OCMR
and status signals from the processor. The ODEC generates all the strobes required
for reading and writing the selected OnCE registers.
16.8 Memory Breakpoint Logic
Memory breakpoints can be set for a particular memory location or on accesses
within an address range. The breakpoint logic contains an input latch for addresses,
registers that store the base address and address mask, comparators, attribute qual-
ifiers, and a breakpoint counter. Figure 16-7 illustrates the basic functionality of the
OnCE memory breakpoint logic. This logic is duplicated to provide two independent
breakpoint resources.
Address comparators can be used to determine where a program may be getting lost
or when data is being written to areas which should not be written. They are also use-
ful in halting a program at a specific point to examine or change registers or memory.
Using address comparators to set breakpoints enables the user to set breakpoints in
RAM or ROM in any operating mode. Memory accesses are monitored according to
the contents of the OCR.
MOTOROLA
16-12
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Freescale Semiconductor, Inc.
Table 16-4 Processor Mode Field Settings
PM[1:0]
00
Processor in normal mode
01
Processor in stop, doze, or wait mode
10
Processor in debug mode
11
Reserved
OnCE™ DEBUG MODULE
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Meaning
MMC2001
REFERENCE MANUAL
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