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Frame — A start bit, followed by a specified number of data or information bits, termi-
nated by one or two stop bits. The number of data or information bits must agree
between the transmitting and receiving devices. The most common frame format is
one start bit followed by eight data bits (LSB first) terminated by one stop bit, for a
total of ten bit times in the frame. The UART optionally provides other data formats as
specified through the control registers.
Break — A frame in which all the bits are logic zero. This includes the stop bit, which
is normally a logic one, as well as the data bits. This kind of a frame is generally sent
to signal the end of a message or the beginning of a new message.
Framing Error — An error condition in which the stop bit of the received frame is
missing. A framing error results when the frame boundaries in the received bit stream
are not synchronized with the receiver bit counter. Framing errors are not always
detected: if a data bit in the expected stop bit time happens to be a logic one, the
framing error may go undetected. A framing error is always present on the receiver
side, when the transmitter is sending breaks. However, if the UART is set up to expect
two stop bits, and only one is received, then this is not a framing error by definition.
Parity Error — An error condition in which the calculated parity of the received data
bits in the frame is different from the parity bit received on the RXD line. Parity error is
only calculated after an entire frame is received.
Overrun Error — An error condition in which the latest character received is ignored
to prevent overwriting an already existing character in the UART receiver FIFO. An
overrun error indicates that the software reading the FIFO is not keeping up with the
actual reception of characters on the RXD line.
11.4 UART Programming Model
This section describes the registers in the UART module. Each UART channel has
the following independent set of registers:
• Three working registers (UCR1, UCR2, USR) that provide all status and control
functions for the UART
• A separate test register (UTS) for those applications that need it
• Bit-rate generator register (UBRG) that controls the UART bit rate
• Separate transmit and receive registers
• Port control register that defines the GPIO functionality of UART pins.
The registers are optimized for a 16-bit bus. For example, all status bits associated
with the received data are available along with the data in a single read. All register
bits are readable (except TX DATA field in the UART transmit register), and most are
read/write.
All registers may be accessed either as a halfword or as a byte. The RX and TX data
registers may also be accessed as 32-bit words. For these registers the upper 16 bits
are forced to zeros.
MMC2001
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
11-5
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