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RXD PIN
Samples
1
1 1
1 1
RT CLK
(16X Bit Rate)
RT CLK
State
Reset RT
Figure 11-14 is similar to the previous case except noise [1] is now closer to the
actual beginning of the start bit. The noise sample and the preceding four logic ones
meet the start qualification requirements. The start verification samples at RT2, RT3,
RT4, RT5, RT6, and RT7 [2] are not all zeros; therefore, the tentative placement of
the start edge is rejected, and the search for the start qualifiers is restarted at [3].
Since there are no more cases of four logic ones in a row [3], the start bit is never
detected. Because the circuit could not locate the start bit, the frame will be received
as a framing error, improperly received, or missed entirely, depending on the data in
the frame and when the start logic synchronized on what it thought was a start bit.
This causes incorrect data reception.
MMC2001
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
[1]
1
0
1
1
1
1 0
[2]
Figure 11-14 Start Bit — Noise Case Two
For More Information On This Product,
Go to: www.freescale.com
No start bit found
Actual Start Bit
0
0
0
0
0
0 0
0
[3]
LSB
0 0
0
0
0
0
0
MOTOROLA
11-21
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