Normal Interrupt Pending Register (Nipnd); Normal Interrupt Pending Register - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

EFx — Enable Fast Interrupt Flag x
This bit enables the corresponding interrupt source to request a fast interrupt.
0 = Disable
1 = Enable
A reset operation clears this bit.
When the enable flag is set and the corresponding interrupt line is asserted, the inter-
rupt controller asserts a fast interrupt request. Enabling an interrupt source that has
an asserted request causes that interrupt to become pending, and a request to the
CPU is asserted if not already outstanding.

10.2.4 Normal Interrupt Pending Register (NIPND)

Access the 32-bit normal interrupt pending register with 32-bit loads only.
NIPND — Normal Interrupt Pending Register
31 30 29 28
NP31 NP30 NP29 NP28
RESET:
0 0 0 0
15 14 13 12
NP15 NP14 NP13 NP12
RESET:
0 0 0 0
Figure 10-4 Normal Interrupt Pending Register
NPx — Normal Interrupt Pending Flag x
This bit indicates a pending normal interrupt request from the corresponding interrupt
source.
0 = No request
1 = Interrupt request pending
When a normal interrupt enable flag is set and the corresponding interrupt line is
asserted, the interrupt controller asserts a normal interrupt request. The normal inter-
rupt pending flags reflect the interrupt input lines which are asserted and are currently
enabled to generate a normal interrupt.
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10-4
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27 26 25 24
NP27 NP26 NP25 NP24
0 0 0 0
11 10 9 8
NP11 NP10 NP9 NP8
0 0 0 0
INTERRUPT CONTROLLER
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23 22 21 20
NP23 NP22 NP21 NP20
0 0 0 0
7 6 5 4
NP7 NP6 NP5 NP4
0 0 0 0
1000000C
19 18 17 16
NP19 NP18 NP17 NP16
0 0 0 0
3 2 1 0
NP3 NP2 NP1 NP0
0 0 0 0
MMC2001
REFERENCE MANUAL