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A single condition code/carry (C) bit is provided for condition testing and for use in
implementing arithmetic and logical operations greater than 32 bits. Typically, the C-
bit is set only by explicit test/comparison operations, not as a side-effect of normal
instruction operation. Exceptions to this rule occur for specialized operations for
which it is desirable to combine condition setting with actual computation.
A 16-entry alternate register file is provided to support low overhead interrupt excep-
tion processing. The CPU supports both vectored and autovectored interrupts.
2.4 Programming Model
The M•CORE programming model is defined separately for two privilege modes:
supervisor and user. Certain operations are not available in user mode.
User programs can only access registers specific to the user mode; system software
executing in the supervisor mode can access all registers, using the control registers
to perform supervisory functions. User programs are thus restricted from accessing
privileged information. The operating system performs management and service
tasks for the user programs by coordinating their activities.
Most instructions execute in either mode, but some instructions that have important
system effects are privileged and can only execute in the supervisor mode. For
instance, user programs cannot execute the stop, doze, or wait instructions. To pre-
vent a user program from entering the supervisor mode except in a controlled man-
ner, instructions that can alter the S bit in the program status register (PSR) are
privileged. The trap #n instructions provide controlled access to operating system
services for user programs. Access to special control registers is also precluded in
user mode.
When the S bit in the PSR is set, the processor executes instructions in the supervi-
sor mode. Bus cycles associated with an instruction indicate either supervisor or user
access depending on the mode.
The processor uses the user programming model during normal user mode process-
ing. During exception processing, the processor changes from user to supervisor
mode. Exception processing saves the current value of the PSR in the EPSR or
FPSR shadow control register and then sets the S bit in the PSR, forcing the proces-
sor into the supervisor mode. To return to the previous operating mode, a system rou-
tine may execute the rte (return from exception) or rfi (return from fast interrupt)
instruction as appropriate, causing the instruction pipeline to be flushed and refilled
from the appropriate address space.
The registers depicted in the programming model (see Figure 2-1) provide operand
storage and control. The registers are partitioned into two levels of privilege: user and
supervisor. The user programming model consists of 16 general-purpose 32-bit regis-
ters, the 32-bit program counter (PC) and the condition/carry (C) bit. The C bit is
implemented as bit 0 of the PSR. This is the only portion of the PSR accessible by the
user. The supervisor programming model consists of 16 additional 32-bit general-pur-
pose registers (the alternate file), as well as a set of status/control registers and
scratch registers. By convention, register R15 serves as the link register for subrou-
tine calls, and register R0 is typically used as the current stack pointer.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
INTEGER CPU
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
2-3
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