Pit Operation; Pit As A "Set-And-Forget" Timer - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

8.192 kHz
(LOW_REFCLK/4)

9.6.1 PIT Operation

The PIT can be written at any time. The value written to the PIT data register (ITDR)
determines the modulus of the timer. Data read from the ITDR is the present value of
the modulus latch. The present counter value is read by reading the PIT alternate
data register (ITADR).
The counter is clocked at a fixed rate of 1/8192 seconds (~122 µs) which is derived
from the 32.768 kHz LOW_REFCLK divided by four.
The internal count registers are clocked using the above divide-by-four
reference. In order to read and write these registers accurately via the
CPU core (which runs from the CPU_CLK), clock synchronization logic
is required internal to the PIT. This logic requires that the CPU clock
frequency (driven from HI_REFCLK) be greater than or equal to the
LOW_REFCLK clock that the counter clocks are derived from.
OSC
OSC/4
Counter
Modulus
Figure 9-13 Starting a Count from an Off State

9.6.2 PIT as a "Set-and-Forget" Timer

This mode of operation is selected when the RLD bit in the PIT control/status register
(ITCSR) is set to a value of one. The counter is not directly writable from the module
data bus; instead, it gets its data from the modulus latch.
MOTOROLA
9-12
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16-Bit Counter
16-Bit Modulus Latch
MMC2001 Peripheral Data Bus
Figure 9-12 PIT Block Diagram
NOTE
0x0005
TIMER/RESET MODULE
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Count = 0
Load Counter
0x0004
0x0005
Interrupt
0x0003
MMC2001
REFERENCE MANUAL