Table of Contents
Advertisement
WS — Word Size
This bit specifies a character length of eight or seven bits (not including start, stop, or
parity bits). When WS is set, the transmitter and receiver are in eight-bit mode. When
WS is cleared, they are in seven-bit mode. The transmitter then ignores B7, and the
receiver sets B7 to zero. This bit can be changed between transmissions or recep-
tions. If it is changed while a transmission or reception is in progress, however, the
length of the current character being transmitted or received is unpredictable.
0 = 7-bit transmit and receive character length
1 = 8-bit transmit and receive character length
At reset, this bit is cleared to zero.
C.9.5 UART BRG Register (UBRGR)
This register specifies the divide ratio of the prescaler in the UART bit clock genera-
tor.
U0BRGR — UART0 BRG Register
U1BRGR — UART1 BRG Register
15
14
13
12
R
0
0
0
0
W
RESET:
CD — Clock Divider
These bits determine the bit clock generator output rate. The CD field is used to pre-
set a 12-bit counter that is decremented at the system clock rate. The value 0x000
produces the maximum clock rate (equal to the system clock). The value 0xFFF pro-
duces the minimum clock rate (divide by 4096).
C.9.6 UART Status Register (USR)
The read/write UART status register indicates the status of the RTS pin, input transi-
tions on the pin, and status of the transmit and receive FIFOs.
U0SR — UART0 Status Register
U1SR — UART1 Status Register
15
14
13
12
TX
R
RTSS TRDY
0
MPTY
W
RESET:
1
0
1
MOTOROLA
C-42
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
11
10
9
8
0
0
0
0
Figure C-40 UART BRG Register
11
10
9
8
0
0
RRDY
0
0
Figure C-41 UART Status Register
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
CD
0
0
0
0
7
6
5
4
0
0
0
RTSD
0
10009084
1000A084
3
2
1
0
0
0
0
0
10009086
1000A086
3
2
1
0
0
0
0
0
MMC2001
REFERENCE MANUAL
Advertisement
Table of Contents
