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8.2.2 Peripheral Behavior in Low-Power Modes
8.2.2.1 UART
In doze mode, the UART stops activity, if so programmed, after finishing the current
character transmission or reception. Clocks are then shut down until the CPU exits
the doze mode. When the doze mode is exited, the UART activates its internal clocks,
and operation continues from the point reached before entering the doze mode.
In stop mode, the UART stops immediately and freezes its operation, register values,
state machines, and external pins. During the stop mode, the UART clocks are shut
down. Coming out of stop mode returns the UART to operation from the mode prior to
stop mode entry. To avoid erroneous operation, ensure that the UART is in an idle
state before stop mode is entered.
8.2.2.2 ISPI
In doze mode, the ISPI stops activity, if so programmed, after finishing the current
character transmission or reception. Clocks are then shut down until the CPU exits
the doze mode. When the doze mode is exited, the ISPI activates its internal clocks,
and operation continues from the point reached before entering the doze mode.
In stop mode, the ISPI stops immediately, aborts any transfer in progress, freezes its
operation and register values, and forgets the state of any transfer in operation. (The
state machine is reset, and the shift register is cleared.) It is assumed that when stop
mode is initiated, there is some other method of shutting down external devices. Dur-
ing the stop mode, the ISPI clocks are shut down. Coming out of stop mode returns
the ISPI to an idle mode. To avoid erroneous operation, ensure that the ISPI is in an
idle state before entering the stop mode.
8.2.2.3 PWM
In doze mode, the PWM channel stops activity, if so programmed, after finishing the
current period. Clocks are then shut down until the CPU exits the doze mode. When
the doze mode is exited, the PWM channel is activated, and operation continues from
the point reached before doze mode was entered.
In stop mode, the PWM stops immediately and freezes its operation, register values,
state machines, and external pins. During the stop mode, the PWM clocks are shut
down. Coming out of stop mode returns the PWM to operation from the state prior to
stop mode entry. To avoid erroneous operation, ensure that the PWM is in an idle
state before entering the stop mode.
8.2.2.4 Interrupt Controller
Because the interrupt controller module logic does not depend on the clock for
asserting an enabled and requested interrupt to the CPU, none of the low-power
modes have any influence on the module's functional behavior. The module registers
will not be accessed by the CPU during the low-power mode states. Once a pending
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
CLOCK MODULE AND LOW-POWER MODES
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
8-5
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