Table of Contents
Advertisement
Interrupt Detection and Processing
7.4.4
Setting the RESET Interrupt Flag for the TMS320C62x/C67x
Figure 7–14. RESET Interrupt Detection and Processing: Pipeline Operation
Clock cycle
0
1
2
RESET
at pin
IF0
IACK
0
0
0
INUM
Execute
packet
n
E1
E2
n+1
DC
E1
n+2
DP
DC
n+3
PR
DP
n+4
PW
PR
n+5
PS
PW
n+6
PG
PS
n+7
PG
Reset ISFP
CPU cycle
0
1
2
† IF0 is set on the next CPU cycle boundary after a 4-clock cycle delay after the rising edge of RESET.
‡ After this point, interrupts are still disabled. All nonreset interrupts are disabled when NMIE = 0. All maskable interrupts are
disabled when GIE = 0.
7-22
RESET must be held low for a minimum of ten clock cycles. Four clock cycles
after RESET goes high, processing of the reset vector begins. The flag for
RESET (IF0) in the IFR is set by the low-to-high transition of the RESET signal
on the CPU boundary. In Figure 7–14, IF0 is set during CPU cycle 15. This
transition is detected on a clock-cycle by clock-cycle basis and is not affected
by memory stalls that might extend a CPU cycle.
3
4
5
6
7
8
0
0
0
0
0
0
Pipeline flush
3
4
5
6
7
8
9
10
11
12
13
14
0
0
0
0
0
0
9
10
11
13
14
12
15
16
17
18
19
20
0
0
0
0
0
0
Cycles 15 – 21:
Nonreset interrupt
processing is disabled
PG
PS
PW
PR
DP
15
16
17
18
19
20
21
22
0
0
}
DC
E1
21
22
Advertisement
Table of Contents
