System Control; Clock And Reset Domains - Texas Instruments TMS320C2810 Data Manual

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
3.7

System Control

This section describes the F281x and C281x oscillator, PLL and clocking mechanisms, the watchdog
function and the low-power modes.
and C281x devices that will be discussed.
C28x CPU
A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
48 Functional Overview
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Figure 3-8
Reset
SYSCLKOUT
Peripheral Reset
(A)
CLKIN
Clock Enables
System
Control
Registers
Peripheral
Registers
Low-Speed Prescaler
Peripheral Low-Speed Peripherals
Registers SCI-A/B, SPI, McBSP
High-Speed Prescaler
Peripheral
High-Speed Peripherals
Registers
HSPCLK
ADC
12-Bit ADC
Registers
Figure 3-8. Clock and Reset Domains
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TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812
shows the various clock and reset domains in the F281x
PLL
Power
Modes
Control
eCAN
LSPCLK
HSPCLK
EV-A/B
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XRS
Watchdog
Block
X1/XCLKIN
OSC
X2
XF_XPLLDIS
I/O
I/O
GPIO
GPIOs
MUX
I/O
16 ADC Inputs