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For 16-bit raw video, the FIFO is configured as a single buffer, as shown in
16-bit data from the VDIN[19-2] bus. The FIFO has a single write pointer and read register (YSRCA).
VDIN[19−2]
1.2.3 Video Display FIFO Configurations
During video display operation, the video port FIFO has one of five configurations depending on the
display mode. For BT.656 operation, a single output is provided on channel A, as shown in
with data output on VDOUT[9-2]. The channel's FIFO is split into Y, Cb, and Cr buffers with separate read
pointers and write registers (YDSTA, CBDST, and CRDST).
For 8-bit raw video, the FIFO is configured as a single buffer as shown in
data on the VDOUT[9-2] half of the bus. The FIFO has a single read pointer and write register (YDSTA).
SPRUEM1 – May 2007
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Figure 1-5. 16-Bit Raw Video Capture FIFO Configuration
Capture FIFO
16
Data Buffer
(5120 bytes)
Figure 1-6. BT.656 Video Display FIFO Configuration
Display FIFO
YDSTA
64
Y Buffer
(2560 bytes)
CBDST
Cb Buffer
64
(1280 bytes)
Cr Buffer
CRDST
64
(1280 bytes)
Figure 1-7. 8-Bit Raw Video Display FIFO Configuration
YDSTA
64
64
8
8
8
Display FIFO
8
Data Buffer
(5120 bytes)
Video Port FIFO
Figure
1-5. The FIFO receives
YSRCA
Figure
VDOUT[9−2]
Figure
1-7. The FIFO outputs
VDOUT[9−2]
Overview
1-6,
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