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BU-65572T
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Manuals and User Guides for DDC BU-65572T. We have
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DDC BU-65572T manual available for free PDF download: Hardware Manual
DDC
BU-65570T
Hardware Manual
DDC BU-65572T Hardware Manual (48 pages)
CompactPCI Interface Card For 1 to 2 Channel MIL-STD-1553 Tester/Simulator
Brand:
DDC
| Category:
Test Equipment
| Size: 0.94 MB
Table of Contents
Table of Contents
4
1 Preface
8
Text Usage
8
Special Handling and Cautions
8
Trademarks
9
Technical Support
9
2 Overview
10
What Is Included in this Manual
10
System Requirements
11
3 Hardware Installation
12
Card Pinout
12
Discrete I/O Connector "J1
13
Figure 1. 40-Pin "J1" Discrete I/O Connector
13
4 Driver Installation
15
Windows 95/98
15
Figure 2. Found New Hardware
15
Figure 3. Search for Driver
16
Figure 4. Specify Driver Location
16
Figure 5. Found Driver
17
Figure 6. Finished Install of Driver
18
Figure 7. Confirm Driver Installation
18
Windows NT 4.0
19
Figure 8. Welcome Screen
20
Figure 9. Software License Agreement
20
Figure 10. Destination Location
21
Figure 11. Component Selection
21
Figure 12. Program Folder Selection
22
Figure 13. Setup Complete
22
Windows 2000
23
Figure 14. Restart Computer
23
Figure 15. Found New Hardware
24
Figure 16. Search for Driver
24
Figure 17. Specify Driver Location
25
Figure 18. Found Driver
26
Figure 19. Finished Install of Driver
26
Hardware Configuration
27
1100 DDC 1553 Card Manager for 95/98/2000
28
Figure 20. Control Panel
28
Figure 21. DDC 1553 Card Manager
29
Figure 22. Card Manager Modify
29
1100 DDC 1553 Card Manager for Windows Nt
31
Figure 23. Control Panel
31
Figure 24. DDC 1553 Card Manager
32
Figure 25. Device Driver Status
32
Figure 26. Modify Device
33
7 Hardware Operation
34
General
34
Bus Controller Mode
34
Minor and Major Frames
34
BC Error Injection
35
Inserting Asynchronous Messages
35
BC Intermessage Routines
36
Response Timeout
36
RT Mode
36
RT Error Injection
37
RT Intermessage Routines
38
BC/RT Data Tables
38
Monitor Mode
39
Interrupts
39
BC Interrupt Generation
40
RT Interrupt Generation
40
Monitor Interrupts
41
Other Features
41
Variable Amplitude Transceiver
41
IRIG-B Support
41
IRIG-B Specifications
42
Figure 27. Sample IRIG Signal Timing
42
Monitor DMA to Host Buffer
43
Software Control of Bus Configuration
43
Discrete Outputs
44
8 Appendix A
46
8 APPENDIX A Acronyms
46
9 Appendix B
46
10 Index
47
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