Mpu Interface - Motorola DragonBall MC68328 User Manual

3.4.2 MPU Interface

One register is associated with the power control block. Figure 3-6 illustrates the bits in the
register.
15 14 13 12
Address: $(FF)FFF206
PC EN
1 = Power-control enabled
0 = Power-control disabled
This bit controls the operation of the power controller. While this bit is low, the clock to the
MC68EC000 is continuously on. While this bit is high, the clock is bursted to the
MC68EC000 under control of the width comparator. An interrupt that can wake up the
MC68EC000 disables the power controller by a negation of this bit. The user's interrupt-
service routine must re-enable this bit to re-enter power-save operation. This bit resets to
zero.
STOP
1 = Stop CPU clock
0 = Normal CPU clock bursts
This bit immediately enters the power-save mode without waiting for the power controller
to cycle through a complete burst period. This bit disables the CPU clock after the bus cy-
cle that follows the next CLK32 rising edge. When the system is to enter the doze mode,
this bit is set. On the next burst period, or interrupt, the clock will restart for its allotted pe-
riod. This bit is reset to zero.
WIDTH
Width of CPU clock bursts. These bits reset to 11111 ($1F).
00000 = 0/31 duty cycle
00001 = 1/31 duty cycle
00010 = 2/31 duty cycle
...
11111 = 31/31 duty cycle
These bits control the width of the CPU clock bursts in 1/31 increments. While the WIDTH
is 1 and the power controller is enabled, the clock is bursted to the CPU at a duty cycle of
1/31. While the WIDTH bits are 1F(hex), the clock is always on. While the WIDTH is zero,
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9
RSVD
Figure 3-6. Power Control Register
Phase-Locked Loop and Power Control
8 7 6 5
PC EN STOP 0
4 3 2 1
WIDTH
Reset Value: $001F
0
3-7