Receiver; Baud Rate Generator; Mpu Interface - Motorola DragonBall MC68328 User Manual

UART

8.2.2 Receiver

The receiver accepts a serial data stream and converts it into a parallel character. It oper-
ates in two modes, 16x and 1x. In 16x mode, it searches for a start bit, qualifies it, then sam-
ples the succeeding data bits at the bit center. Jitter tolerance and noise immunity are
provided by sampling at a 16x rate and using a voting technique to clean up the samples. In
1x mode, RXD is sampled on each rising edge of the bit clock.
After locating the start bit, the data bits, parity bit (if enabled), and stop bits are shifted in. If
parity is enabled, it is checked and its status is reported in the receiver register. Similarly,
frame errors and breaks are checked and reported. When the host is ready to read a new
character, RTS is asserted and an interrupt is posted (if enabled). When the receiver register
is read as a 16-bit word, the 68000 core reads the complete FIFO status, the four status bits,
and the received character byte. The RTS pin can be configured as an output, which indi-
cates the receiver is ready for data or software can directly control the pin.
As with the transmitter, the receiver FIFO is flexible. If a user's software has a short interrupt
latency, the FIFO FULL interrupt can be enabled. One space is available in the FIFO when
this interrupt is generated. By reading the receive register as a word, the FIFO status is pre-
sented to the M68EC000 along with the data. If the FIFO status indicates that data remains
in the FIFO, the FIFO can then be emptied byte-by-byte. If the software has a longer latency,
the FIFO HALF interrupt is used. This interrupt is generated when 4 bytes have been
entered into the FIFO. If the FIFO is not needed, the DATA READY interrupt is used. This
interrupt is generated whenever one or more characters are present in the FIFO.
While the IrDA interface is enabled, the receiver expects narrow pulses for each 0 bit
received; otherwise, normal NRZ is expected. An IrDA transceiver, external to the MC68328
processor, transforms the infrared signal to an electrical signal.

8.2.3 Baud Rate Generator

The baud generator provides the bit clocks to the transmitter and receiver blocks. It consists
of a prescaler that divides the clock source by any integer between 2 and 64. The output of
n
the prescaler is then further divided by a 2 divider. Eight taps are available at 1, 2, 4, 8, 16,
32, 64, and 128. The selected tap is the 16x clock for the receiver. This clock is further
divided by 16 to provide the 50% duty cycle 1x clock to the transmitter. The baud generator
is flexible enough to provide almost any "standard" baud rate from a variety of clock frequen-
cies.The system default frequency of 16.58 MHz provides a good base for generating stan-
dard baud rates within 0.01%.
The baud generator master clock source can either be the system clock or it can be provided
through the GPIO pin. By configuring port M bit 7 as an input and setting the baud source
bit to 1, an external signal can directly drive the baud generator. For synchronous applica-
tions, the GPIO pin can be configured to serve as an input or output for the 1x bit-clock.

8.2.4 MPU Interface

The MPU interface contains all status/control registers and all miscellaneous logic. This
block directly connects to the internal 68000 bus and provides address decode for three
address lines and a full 16-bit read/write port. The interrupt line is the logical-OR of the 8
8-4 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL MOTOROLA