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2.2.3.1
PCI Express Bifurcated Mode
When bifurcated, the signals which had previously been assigned to Lanes 15:8 of the
single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary Port. This
assignment applies whether the lane numbering is reversed or not. PCI Express Port 0
is mapped to PCI Device 1 and PCI Express Port 1 is mapped to PCI Device 6.
2.2.3.2
Static Lane Numbering Reversal
Does not support dynamic lane reversal, as defined (optional) by the PCI Express Base
Specification.
PCI Express 1x16 configuration:
•
Normal (1x16): PEG_RX[15:0]; PEG_TX[15:0]
•
Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15]
2.3
DMI
DMI connects the processor and the PCH chip-to-chip. DMI2 is supported. The DMI is
similar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth in each
direction.
Note:
Only DMI x4 configuration is supported.
2.3.1
DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.3.2
Processor/PCH Compatibility Assumptions
The processor is compatible with the PCH and is not compatible with any previous
(G)MCH or ICH products.
2.3.3
DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
28
Interfaces
Datasheet
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