AMD Elan SC520 Manuals

Manuals and User Guides for AMD Elan SC520. We have 1 AMD Elan SC520 manual available for free PDF download: User Manual

AMD Elan SC520 User Manual (444 pages)

Brand: AMD | Category: Microcontrollers | Size: 7 MB

Table of Contents

5
Table of Contents

21
- Preface
  23
  - Intended Audience
    23
  - Introduction
    23
  - Overview of this Manual
    23
  - Purpose of this Manual
    23
  - Élan™Sc520 Microcontroller
    23
  - AMD Documentation
    24
  - Related Documents
    24
  - Additional Information
    25
  - Documentation Conventions
    25
  - Table 0-1 Documentation Notation
    25
- Index
  26
- Chapter 1 Architectural Overview
  
  29
- Chapter 2 Pin Information
  
  43
- Chapter 3 System Initialization
  
  57
- Chapter 4 System Address Mapping
  
  79
  - Overview
    79
  - Registers
    80
  - Operation
    81
  - Table 4-3 Bus Master Address Spaces
    81
    
    Programming External Memory, Buses, and Chip Selects
    82
    
    Programmable Address Region (PAR) Registers
    83
    
    Figure 4-1 Programmable Address Region (PAR) Register Format
    84
    
    Figure 4-2 System Memory Map
    85
    
    Memory Space
    85
    
    Rom/Flash Space
    86
    
    SDRAM Space
    86
    
    GP Bus Memory Space
    87
    
    Memory-Mapped Configuration Region (MMCR) Registers Space
    87
    
    PCI Bus Memory Space
    87
    
    Configuration Base Address (CBAR) Register
    88
    
    I/O Space
    88
    
    Figure 4-3 System I/O Map
    89
    
    PCI Configuration Space
    89
    
    PC/AT-Compatible I/O Peripherals Region
    90
    
    PCI I/O Space
    90
    
    Table 4-5 PC/AT Peripherals I/O Map
    91
    
    Configuration Information
    92
    
    Configuring Rom/Flash Space
    92
    
    Configuring SDRAM Address Space
    92
    
    GP Bus I/O Region
    92
    
    Configuring GP Bus Peripheral Space
    93
    
    Configuring the Élansc520 Microcontroller for Windows® Compatibility
    94
    
    Configuring PCI Bus Devices
    95
    
    Interrupts
    95
    
    Software Considerations
    95
  - Initialization
    98
- Chapter 5 Clock Generation and Control
  
  99
  - Overview
    99
  - Block Diagram
    100
  - System Design
    101
  - Figure 5-2 System Clock Distribution Block Diagram
    101
  - Table 5-2 Clock Signals Shared with Other Interfaces
    101
    
    Clock Pin Loading
    102
    
    At 33.333 Mhz
    103
    
    Figure 5-3 Bypassing the 32.768-Khz Oscillator
    103
    
    Table 5-3 Timing Error as It Translates to Clock Accuracy
    103
  - Registers
    104
  - Figure 5-4 Bypassing the 33-Mhz Oscillator
    104
  - Table 5-4 Clock Control Registers-Memory-Mapped
    104
  - Operation
    105
  - GP-DMA Controller
    106
  - Initialization
    107
  - Figure 5-5 Clock Routing for the CLKTEST Pin
    107
- Chapter 6 Reset Generation
  
  109
  - Overview
    109
  - Figure 6-1 Reset Controller Block Diagram
    110
  - System Design
    110
  - Registers
    111
  - Operation
    111
  - Table 6-1 Reset Generation Registers-Memory-Mapped
    111
  - Table 6-2 Reset Generation Registers-Direct-Mapped
    111
    
    Cpu
    112
    
    System Reset
    112
    
    Table 6-3 Élansc520 Microcontroller Reset Sources
    112
    
    General-Purpose Timers
    113
    
    GP Bus
    113
    
    GP-DMA Controller
    113
    
    Programmable Interval Timer
    113
    
    Software Timer
    113
    
    Table 6-4 States of Cores after System Reset
    113
    
    Watchdog Timer
    113
    
    Figure 6-2 PRGRESET Timing
    114
    
    System Reset with SDRAM Retention
    114
    
    PCI Reset
    115
    
    RTC Reset
    115
    
    Soft CPU Reset
    115
    
    Clocking Considerations
    116
    
    CPU A20 Gate Support
    116
    
    Determining Reset Sources
    116
    
    Software Considerations
    116
    
    Figure 6-3 Power-On Reset Sequence of Events
    117
    
    Latency
    117
- CHAPTER 7 Am5
  
  119
  - Am5 X 86 ® CPU
    119
  - Overview
    119
  - Registers
    119
  - Figure 7-1 Am5 X 86 CPU Block Diagram
    120
  - Operation
    121
    
    Floating Point Unit (FPU)
    121
    
    Cache Memory Management
    122
    
    Clocking Considerations
    122
    
    Table 7-3 Cache Configuration Options
    122
    
    Interrupts
    123
    
    Latency
    123
  - Initialization
    123
    
    Hard CPU Reset
    123
    
    Soft CPU Reset
    123
- Chapter 8 System Arbitration
  
  125
  - Overview
    125
  - Block Diagram
    125
  - Registers
    126
  - Figure 8-1 System Arbitration Block Diagram
    126
  - Table 8-1 System Arbitration Registers-Memory-Mapped
    126
  - Operation
    127
    
    Nonconcurrent Arbitration Mode
    127
    
    Operating Modes
    127
    
    Concurrent Arbitration Mode
    128
    
    CPU Arbitration Protocol
    129
    
    CPU Bus Arbiter
    129
    
    Figure 8-2 Skipped Master Example
    129
    
    Accessing the PCI Host Bridge Target
    130
    
    CPU Cache Snooping
    130
    
    Figure 8-3 CPU Bus Rotating Priority Queue
    130
    
    Arbitration During Clock Speed Changes
    131
    
    GP Bus DMA Arbitration
    131
    
    PCI Bus Arbiter
    131
    
    PCI Bus Arbitration Protocol
    132
    
    Figure 8-4 External PCI Master Arbitration Queues
    133
    
    Figure 8-5 Host Bridge Master Arbitration Queue
    133
    
    Bus Parking
    134
    
    Rearbitration
    134
    
    Bus Cycles
    135
    
    CPU Bus Arbitration
    135
    
    Figure 8-6 CPU Bus Arbitration
    135
    
    CPU Bus Cache Write-Back
    136
    
    Figure 8-7 CPU Bus Cache Write-Back
    137
    
    CPU-To-PCI Cycle
    138
    
    Figure 8-8 CPU-To-PCI Cycle
    138
    
    Figure 8-8 Figure
    138
    
    Figure 8-9 PCI Bus Arbitration
    139
    
    PCI Bus Arbitration
    139
    
    Figure 8-10 PCI Bus Concurrent Mode Arbitration Parking
    140
    
    PCI Bus Arbitration Parking
    140
    
    Figure 8-11 Nonconcurrent Mode Arbitration
    142
    
    Nonconcurrent Mode Arbitration
    142
    
    Interrupts
    143
    
    Software Considerations
    143
    
    Figure 8-12 Simple Rotating Priority Queue
    144
    
    Latency
    144
    
    Simple Rotating Priority Latency
    144
    
    CPU Latency
    145
    
    High-Priority Queue Latency
    145
    
    Low-Priority Queue Latency
    145
    
    Nonconcurrent Arbitration Mode Latency
    145
    
    Concurrent Arbitration Mode Bus Parking Latency
    146
    
    Concurrent Arbitration Mode Latency
    146
  - Initialization
    146
- Chapter 9 Pci Bus Host Bridge
  
  149
- Chapter 10 Sdram Controller
  
  179
  - Overview
    179
  - Block Diagram
    179
  - System Design
    179
  - Figure 10-1 SDRAM Controller Block Diagram
    180
  - Figure 10-2 Detailed Block Diagram of SDRAM Controller
    181
  - Figure 10-3 SDRAM Bank Configuration
    182
    
    Figure 10-4 Example Configuration of a 168-Pin SDRAM DIMM
    183
    
    SDRAM Pins
    183
    
    SDRAM Clocking
    184
    
    Table 10-1 SDRAM Clock Loading Estimates Based on Device Width
    184
    
    Figure 10-5 SDRAM Clock Generation
    185
    
    SDRAM Loading
    186
    
    Table 10-2 Estimated Capacitance (4-Bit SDRAM Devices)
    186
    
    Table 10-3 Estimated Capacitance (8-Bit SDRAM Devices)
    186
    
    Table 10-4 Estimated Capacitance (16-Bit SDRAM Devices)
    187
    
    Table 10-5 Estimated Capacitance (32-Bit SDRAM Devices)
    187
  - Registers
    188
  - Operation
    189
    
    SDRAM Support
    189
    
    SDRAM Addressing
    190
    
    Table 10-10 SDRAM
    190
    
    Table 10-7 Address Mapping to Max Signals for SDRAM Devices
    190
    
    Supported SDRAM Devices
    191
    
    Table 10-8 SDRAM Devices Supported with Column Boundary Specification
    191
    
    Table 10-9 Column Address Configuration Settings for SDRAM
    193
    
    Error Correction Code (ECC)
    194
    
    Page Size
    194
    
    Buffering
    195
    
    Operation Mode Select
    196
    
    Refresh Control
    196
    
    SDRAM Control Configuration
    196
    
    Table 10-11 SDRAM Refresh Rates
    196
    
    Write Buffer Test Mode
    196
    
    CAS Latency (C L )
    198
    
    SDRAM Timing Configuration
    198
    
    RAS Precharge
    199
    
    RAS-To-CAS Delay (TRCD )
    199
    
    RAS-To-RAS or Auto-Refresh-To-RAS (TRC )
    199
    
    Bus Cycles
    200
    
    Minimum RAS (tras )
    200
    
    SDRAM Burst Read Cycle
    200
    
    SDRAM Write Cycle
    201
    
    ECC SDRAM Cycles
    202
    
    Figure 10-10 SDRAM Burst Read Cycle with ECC Enabled
    203
    
    SDRAM Auto Refresh Cycle
    204
    
    Interrupts
    205
    
    SDRAM Mode Register Access Cycles
    205
    
    Buffer Disabling During SDRAM Configuration
    206
    
    ECC Errors
    206
    
    Latency
    206
    
    Software Considerations
    206
    
    Write Protection
    206
  - Initialization
    207
    
    Programmable Reset
    207
    
    Operation Mode Select
    208
    
    SDRAM Device Initialization
    208
    
    Auto Refresh Command
    209
    
    Mode Register Programming
    209
    
    NOP Command
    209
    
    Precharge Command
    209
    
    Table 10-12 Load Mode Register Settings
    209
    
    Boot Process
    210
    
    SDRAM Sizing Algorithm
    210
    
    Determining the Number of Columns for an External Bank
    211
    
    Determining the Number of Internal Banks
    212
    
    Determining the True External Bank Ending Address
    213
- Chapter 11 Write Buffer and Read Buffer
  
  215
  - Overview
    215
  - Block Diagram
    216
  - System Design
    217
  - Registers
    218
  - Operation
    218
  - Table 11-1 SDRAM Signals Shared with Other Interfaces
    218
  - Table 11-2 SDRAM Buffer Control Registers-Memory-Mapped
    218
    
    Write Buffer
    219
    
    Write Buffer Disabled
    219
    
    Write Buffer Enabled
    219
    
    Figure 11-3 Write Buffer Merging Example
    221
    
    Figure 11-4 Write Buffer Collapsing Example
    222
    
    Write Buffer Watermark
    223
    
    Read Buffer and the Read-Ahead Feature
    224
    
    Read-Ahead Feature Disabled
    224
    
    Read-Ahead Feature Enabled
    224
    
    DMA Considerations
    225
    
    PCI Considerations
    226
    
    Read Cycles
    226
    
    Write Cycles
    226
    
    SDRAM Bandwidth Improvements
    227
    
    Software Considerations
    227
    
    Figure 11-6 Bus Thrashing with Write Buffer Disabled and Enabled
    228
  - Initialization
    229
- Chapter 12 Rom/Flash Controller
  
  231
  - Overview
    231
  - Table 12-1 Rom/Flash Data Bus Connection Options
    231
  - Block Diagram
    232
  - System Design
    232
    
    Table 12-2 ROM Signals Shared with Other Interfaces
    233
    
    Voltage Isolation
    233
    
    Figure 12-2 Voltage Isolation Examples
    234
  - Registers
    235
  - Operation
    235
    
    ROM Support
    235
    
    Table 12-3 ROM Controller Registers-Memory-Mapped
    235
    
    Supported Device Types
    236
    
    Access Timing
    237
    
    Operating Mode
    237
    
    ROM Control and Timing Configuration
    237
    
    ROM Location
    237
    
    ROM Width
    237
    
    Bus Cycles
    239
    
    Single CPU Read Access
    239
    
    Table 12-4 Example: ROM Access Timing and Wait States
    239
    
    Table 12-5 Accesses and ROM Width
    239
    
    Page-Mode Read Access
    240
    
    Cache-Line Fill
    241
    
    Writing to Flash Devices
    241
    
    Address Decoding
    242
    
    Programming Flash Memory
    242
    
    Software Considerations
    242
    
    Latency
    243
  - Initialization
    244
  - Table 12-6 Cfgx Pinstrap Configuration Options for BOOTCS
    244
- Chapter 13 General-Purpose Bus Controller
  
  245
  - Overview
    245
  - Block Diagram
    245
  - System Design
    245
    
    Figure 13-1 GP Bus Controller System Block Diagram
    246
    
    Table 13-1 GP Bus Signals Shared with Other Interfaces
    247
    
    GP Bus Loading
    248
    
    Voltage Translation
    248
  - Registers
    249
  - Operation
    250
    
    Programmable Bus Interface Timing
    251
    
    Timing Requirements
    251
    
    Using GP Bus Echo Mode with Programmable Timing
    252
    
    Using GPRDY with Programmable Timing
    252
    
    Chip Select Qualification
    253
    
    Data Sizing and Unaligned Accesses
    253
    
    I/O-Mapped and Memory-Mapped Device Support
    253
    
    GP Bus Echo Mode
    254
    
    Sharing the Address and Data Bus with the Rom/Flash Controller
    254
    
    Compatibility with Common ISA Devices
    255
    
    DMA Interface
    255
    
    Usage Scenarios
    255
    
    Table 13-4 Cross-Reference Table of ISA Signals and GP Bus Signals
    256
    
    Interfacing with a Super I/O Controller
    257
    
    Interfacing with an AMD Enhanced
    258
    
    Figure 13-7 Élansc520 Microcontroller Interfacing with an Am85C30
    259
    
    8-Bit Data Access of an 8-Bit I/O Device
    260
    
    Bus Cycles
    260
    
    16-Bit Data Access of a 16-Bit I/O Device
    261
    
    16-Bit Data Access of an 8-Bit I/O Device
    261
    
    32-Bit Data Access of a 16-Bit I/O Device
    262
    
    32-Bit Data Access of an 8-Bit I/O Device
    262
    
    8-Bit Data Access of a 16-Bit I/O Device
    263
    
    GPIOCS16 and GPMEMCS16 Timing
    263
    
    Wait States
    264
    
    8/16-Bit GP Bus Width
    265
    
    Interrupts
    265
    
    Latency
    265
    
    Noncacheable GP Bus
    265
    
    Slow GP Bus Cycles
    265
  - Initialization
    266
- Chapter 14 Gp Bus Dma Controller
  
  267
  - Overview
    267
  - Block Diagram
    267
  - Figure 14-1 GP-DMA Controller Block Diagram
    268
  - System Design
    269
  - Registers
    270
    
    Memory-Mapped Registers
    270
    
    Direct-Mapped Registers
    272
    
    Table 14-3 GP-DMA Controller Registers—Direct-Mapped
    273
  - Operation
    274
    
    GP-DMA Transfers
    274
    
    GP-DMA Initiators
    275
    
    GP-DMA Channel Mapping
    276
    
    Normal GP-DMA Mode
    276
    
    Operating Modes
    276
    
    Addressing GP-DMA Channels
    277
    
    Addressing in Normal GP-DMA Mode
    277
    
    Enhanced GP-DMA Mode
    277
    
    Addressing in Enhanced GP-DMA Mode
    278
    
    Demand Transfer Mode
    278
    
    GP-DMA Transfer Modes
    278
    
    Single Transfer Mode
    278
    
    Block Transfer Mode
    279
    
    Transfer Types
    279
    
    Automatic Initialization Control
    280
    
    Buffer Chaining
    281
    
    Priority
    281
    
    Bus Cycles
    282
    
    GP Bus I/O to SDRAM
    282
    
    GP Bus Echo Mode
    283
    
    GP-DMA Read with Cache Hit
    283
    
    Clocking Considerations
    284
    
    Interrupts
    284
    
    Latency
    284
    
    Nonpreemptive Latency
    284
    
    Software Considerations
    284
    
    Preemptive Latency
    285
  - Initialization
    285
    
    Configuring an 8-Bit Channel in Normal GP-DMA Mode
    285
    
    Example Configurations
    285
    
    Configuring a 16-Bit Channel in Normal GP-DMA Mode
    286
    
    Configuring an 8-Bit Channel in Enhanced GP-DMA Mode
    286
    
    Configuring a 16-Bit Channel in Enhanced GP-DMA Mode
    287
- Chapter 15 Programmable Interrupt Controller
  
  289
  - Overview
    289
    
    Block Diagram
    290
    
    Figure 15-1 Programmable Interrupt Controller (PIC) Block Diagram
    291
    
    Registers
    292
    
    Table 15-3 Programmable Interrupt Controller Registers—Direct-Mapped
    294
    
    Operation
    295
  - Interrupt Sources
    296
  - Figure 15-2 Interrupt Sources
    297
  - Interrupt Source Routing
    298
    
    Figure 15-3 Interrupt Source Routing
    299
    
    PC/AT Compatibility
    300
    
    Disabling the Slave Controllers
    301
  - Non-Maskable Interrupts and Routing
    302
  - Figure 15-4 NMI Routing
    303
  - Priority Types
    304
    
    PC/AT Configuration
    306
    
    Disabling the Slave Controllers
    307
    
    Initialization
    308
- Chapter 16 Programmable Interval Timer
  
  309
  - Registers
    310
  - Operation
    311
  - PIT Channel 2
    312
    
    Mode 2: Rate Generator
    313
    
    Clocking Considerations
    314
    
    Initialization
    315
- Chapter 17 General-Purpose Timers
  
  317
  - Registers
    318
  - Operation
    319
  - GP Timer 2
    320
    
    Configuration Information
    321
    
    External Clock
    322
    
    Initialization
    324
- Chapter 18 Software Timer
  
  325
  - Registers
    326
  - Configuration Information
    327
- Chapter 19 Watchdog Timer
  
  329
  - Registers
    330
  - Operation
    331
  - Interrupt Request Generation
    332
    
    Interrupts
    333
    
    Initialization
    334
- Chapter 20 Real-Time Clock
  
  335
  - Figure 20-1 Real-Time Clock Block Diagram
    336
  - System Design
    337
  - System Without an External Backup Battery
    338
  - Selecting and Interfacing a 32.768-Khz Crystal
    339
    
    Registers
    340
    
    Operation
    341
    
    Programming the Date and Time
    342
    
    Using the Alarm Function
    343
    
    Software Considerations
    344
    
    RTC Reset
    345
- Chapter 21 Uart Serial Ports
  
  347
  - System Design
    348
  - Registers
    349
  - Table 21-4 UART Registers—Direct-Mapped
    350
  - Operation
    351
  - Data Transmission
    352
    
    Compatible UART Mode
    353
  - Error Handling
    354
    
    Configuration Information
    355
    
    DMA Interface
    356
    
    Table 21-6 UART Interrupt Programming Summary
    357
    
    Serial Port Interrupts
    358
    
    Interrupt Disable
    359
- Chapter 22 Synchronous Serial Interface
  
  361
  - Registers
    362
  - Operation
    363
  - Figure 22-2 SSI Four-Pin Interface
    364
  - Configuration Information
    365
    
    Bit Read Cycle
    366
    
    Burst, 16-Bit, and 32-Bit Cycles
    367
    
    Software Considerations
    368
- Chapter 23 Programmable Input/Output
  
  369
  - System Design
    370
    
    Table 23-1 PIO Signals Shared with Other Interfaces
    371
    
    Registers
    372
    
    Configuration Information
    373
  - Initialization
    374
- Chapter 24 System Test and Debugging
  
  375
  - Loading
    376
    
    Operation
    377
    
    Using the System Test Mode Interface
    378
    
    SDRAM Read Cycle in System Test Mode
    379
    
    Tracing Transactions on the GP Bus Interface
    380
    
    Write Buffer Test Mode
    381
    
    SDRAM Write Cycle in Write Buffer Test Mode
    382
    
    Figure 24-4 Write Buffer Test Mode Timing During a SDRAM Read Cycle (Page Miss)
    383
    
    Microcontroller
    384
    
    Software Considerations
    385
    
    Initialization
    386
- Chapter 25 Boundary Scan Test Interface
  
  387
  - Registers
    388
    
    Instruction Register
    389
    
    Configuration Information
    390
    
    Bypass Path
    391
  - Serial Debug Port Data Register
    399
    
    Test Access Port (TAP) Controller
    400
    
    TAP Controller States
    401
    
    Rising Edge of JTAG_TCK
    403
    
    When the TAP Controller Is in this State and a Rising Edge Is Applied to JTAG_TCK, the
    403
    
    Bus Cycles
    404
    
    If JTAG_TMS Is Low
    404
    
    The Controller Remains in this State as Long as JTAG_TMS Is Low. When JTAG_TMS Goes
    404
    
    The Scanning Process. if JTAG_TMS Is Held Low and a Rising Edge Is Applied to JTAG_TCK
    404
    
    This State. the Instruction Does Not Change in this State
    404
    
    When the TAP Controller Is in this State and a Rising Edge Is Applied to JTAG_TCK, the
    404
    
    Figure 25-5 Test Logic Operation: Data Scan
    405
    
    Clocking Considerations
    406
- CHAPTER 26 Amdebug™ TECHNOLOGY
  
  407
  - Block Diagram
    408
  - Figure 26-2 12-Pin Connector Format
    409
  - Mechanical Specifications for the Target Connector
    410
  - Locating the Connector on the Target System
    411
    
    Operation
    412
  - Software Performance Profiling
    413

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AMD Elan SC520 Manuals

AMD Elan SC520 User Manual (444 pages)

Table of Contents

Table of Contents

Table of Contents

Chapter 1 Architectural Overview

Chapter 2 Pin Information

Chapter 3 System Initialization

Chapter 4 System Address Mapping

Chapter 5 Clock Generation and Control

Chapter 6 Reset Generation

CHAPTER 7 Am5

Chapter 8 System Arbitration

Chapter 9 Pci Bus Host Bridge

Chapter 10 Sdram Controller

Chapter 11 Write Buffer and Read Buffer

Chapter 12 Rom/Flash Controller

Chapter 13 General-Purpose Bus Controller

Chapter 14 Gp Bus Dma Controller

Chapter 15 Programmable Interrupt Controller

Chapter 16 Programmable Interval Timer

Chapter 17 General-Purpose Timers

Chapter 18 Software Timer

Chapter 19 Watchdog Timer

Chapter 20 Real-Time Clock

Chapter 21 Uart Serial Ports

Chapter 22 Synchronous Serial Interface

Chapter 23 Programmable Input/Output

Chapter 24 System Test and Debugging

Chapter 25 Boundary Scan Test Interface

CHAPTER 26 Amdebug™ TECHNOLOGY

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