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AMD SR5650 Manuals
Manuals and User Guides for AMD SR5650. We have
1
AMD SR5650 manual available for free PDF download: Data Book
AMD SR5650 Data Book (78 pages)
Brand:
AMD
| Category:
Motherboard
| Size: 0 MB
Table of Contents
Table of Contents
3
Chapter 1: Overview
11
Introducing the SR5650
11
SR5650 Features
11
CPU Interface
11
PCI Express® Interface
11
A-Link Express II Interface
11
Multiple Processor Support
12
Multiple Northbridge Support
12
Power Management Features
12
PC Design Guide Compliance
12
Test Capability Features
12
Packaging
12
Software Features
12
Device ID
13
Branding Diagrams
13
Figure 1-1 SR5650 Branding Diagram for A21 Production ASIC (Eutectic Part)
13
Figure 1-2 SR5650 Branding Diagram for A21 Production ASIC (Lead Free Part)
13
Table 1-1 Device Ids for the SR5690/5670/5650 Chipset Family
13
Conventions and Notations
14
Pin Names
14
Pin Types
14
Numeric Representation
14
Hyperlinks
14
Acronyms and Abbreviations
14
Table 1-2 Pin Type Codes
14
Table 1-3 Acronyms and Abbreviations
14
SR5650 Databook
16
Chapter 2: Functional Descriptions
17
Hypertransport™ Interface
17
Overview
17
Figure 2-1 SR5650 Internal Blocks and Interfaces
17
Figure 2-2 Hypertransport™ Interface Block Diagram
18
Hypertransport™ Flow Control Buffers
19
Figure 2-3 SR5650 Hypertransport™ Interface Signals
19
Table 2-1 SR5650 Hypertransport™ Flow Control Buffers
19
Iommu
20
Multiple Northbridge Support
20
Interrupt Handling
20
Legacy Intx Handling
20
Non-SB IOAPIC Support
20
Integrated IOAPIC Support
21
MSI Interrupt Handling and MSI to HT Interrupt Conversion
21
Internally Generated Interrupts
21
IOMMU Interrupt Remapping
21
Interrupt Routing Architecture
21
Figure 2-4 Interrupt Routing Paths in Legacy Mode
22
Figure 2-5 Interrupt Routing Paths in Legacy Mode with Integrated IOAPIC
22
RAS Features
23
Parity Protection
23
SERR_FATAL# and NON_FATAL_CORR# Pins
23
Figure 2-6 Interrupt Routing Path in MSI Mode
23
NMI# and SYNCFLOODIN
24
Suggested Platform Level RAS Sideband Signal Connections
24
Error Reporting and Logging
25
Figure 2-7 Suggested Platform Level RAS Sideband Signal Connections
25
Table 2-2 Types of Errors Detectable by the SR5650 AER Implementation
26
Interrupt Generation on Errors
27
Poisoned Data Support
27
Pcie® Link Disable State
27
Table 2-3 Types of Hypertransport™ Errors Supported by the SR5650
27
HT Syncflood Based on Pcie® Error
28
PCI Express
28
Pcie® Ports
28
Pcie® Reset Signals
28
External Clock Chip
28
Table 2-4: Possible Configurations for the PCI Express® General Purpose Links
28
Table 3-2: PCI Express® Interface for General Purpose External Devices
29
Table 3-4: Miscellaneous PCI Express® Signals
29
Chapter 3 : Pin Descriptions and Strap Options
30
Pin Assignment Top View
30
SR5650 Interface Block Diagram
32
CPU Hypertransport™ Interface
32
Figure 3-1 SR5650 Interface Block Diagram
32
Table 3-1 Hypertransport™ Interface
32
PCI Express Interfaces
33
PCI Express® Interface for General Purpose External Devices
33
A-Link Express II Interface to Southbridge
33
Table 3-3 1 X 4 Lane A-Link Express II Interface for Southbridge
33
Clock Interface
34
Power Management Pins
34
Table 3-5 Clock Interface
34
Table 3-6 Power Management Pins
34
Miscellaneous Pins
35
Power Pins
35
Table 3-7 Miscellaneous Pins
35
Table 3-8 Power Pins
35
Ground Pins
37
Table 3-9 Ground Pins
37
Strapping Options
38
Table 3-10 Strap Definitions for the SR5650
38
Chapter 4: Timing Specifications
39
Hypertransport™ Bus Timing
39
Hypertransport™ Reference Clock Timing Parameters
39
Table 4-2 Timing Requirements for Hypertransport™ Reference Clock (100Mhz)
39
OSCIN Reference Clock Timing Parameters
40
Power Rail Sequence
40
Table 4-3 Timing Requirements for OSCIN Reference Clock (14.3181818Mhz)
40
Table 4-4 Power Rail Groupings for the SR5650
40
Figure 4-1 SR5650 Power Rail Power up Sequence
41
Power up
41
Table 4-5 SR5650 Power Rail Power-Up Sequence
41
Power down
42
Chapter 5: Electrical Characteristics and Physical Data
43
Electrical Characteristics
43
Maximum and Minimum Ratings
43
DC Characteristics
43
Table 5-1 Power Rail Maximum and Minimum Voltage Ratings
43
Table 5-2 Power Rail Current Ratings
43
SR5650 Thermal Characteristics
44
SR5650 Thermal Limits
44
Table 5-3 DC Characteristics for 1.8V GPIO Pads
44
Table 5-5 SR5650 Thermal Limits
44
Thermal Diode Characteristics
45
Package Information
46
Figure 5-2 SR5650 692-Pin FCBGA Package Outline
46
Table 5-6 SR5650 692-Pin FCBGA Package Physical Dimensions
46
Figure 5-3 SR5650 Ball Arrangement (Bottom View)
47
Pressure Specification
47
Board Solder Reflow Process Recommendations
48
Table 5-7 Recommended Board Solder Reflow Profile - Rohs/Lead-Free Solder
48
Figure 5-4 Rohs/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile
49
Chapter 6: Power Management and ACPI
51
ACPI Power Management Implementation
51
Table 6-1 ACPI States Supported by the SR5650
51
Advanced Micro Devices, Inc
52
Chapter 7: Testability
53
Test Capability Features
53
Test Interface
53
XOR Tree
53
Brief Description of an XOR Tree
53
Table 7-1 Pins on the Test Interface
53
Description of the XOR Tree for the SR5650
54
XOR Tree Activation
54
Figure 7-1 XOR Tree
54
Table 7-2 Example of an XOR Tree
54
XOR Tree for the SR5650
55
Table 7-3 SR5650 XOR Tree
55
VOH/VOL Test
56
Brief Description of a VOH/VOL Tree
56
VOH/VOL Tree Activation
57
Figure 7-2 Sample of a Generic VOH/VOL Tree
57
Table 7-4 Truth Table for the VOH/VOL Tree Outputs
57
VOH/VOL Pin List
58
Table 7-5 SR5650 VOH/VOL Tree
58
Appendix A Pin Listings
61
SR5650 Pin Listing Sorted by Ball Reference
62
SR5650 Pin Listing Sorted by Pin Name
69
Appendix B Revision History
77
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