Errata - Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification

Errata

Errata
AAJ1. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set
Problem:
the Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated
by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001
0100, in the MCi_Status register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register
may not be an accurate indication of multiple occurrences of DTLB errors.
There is no other impact to normal processor functionality.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ2. Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
When a debug exception is signaled on a load that crosses cache lines with
Problem:
data forwarded from a store and whose corresponding breakpoint enable flags
are disabled (DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be
incorrect.
Implication: The debug exception DR6.B0-B3 flags may be incorrect for the
load if the corresponding breakpoint enable flag in DR7 is disabled.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ3. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
If the target linear address range for a MONITOR or CLFLUSH is mapped to
Problem:
the local xAPIC's address space, the processor will hang.
Implication: When this erratum occurs, the processor will hang. The local
xAPIC's address space must be uncached. The MONITOR instruction only
functions correctly if the specified linear address range is of the type write-
back. CLFLUSH flushes data from the cache. Intel has not observed this
erratum with any commercially available software.
Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address
space.
®
Intel Core™ i7 processor
Specification Update
19