Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 35

Errata
AAJ47. xAPIC Timer May Decrement Too Quickly Following an Automatic
Reload While in Periodic Mode
When the xAPIC Timer is automatically reloaded by counting down to zero in
Problem:
periodic mode, the xAPIC Timer may slip in its synchronization with the
external clock. The xAPIC timer may be shortened by up to one xAPIC timer
tick.
Implication: When the xAPIC Timer is automatically reloaded by counting
down to zero in periodic mode, the xAPIC Timer may slip in its
synchronization with the external clock. The xAPIC timer may be shortened by
up to one xAPIC timer tick.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ48. Certain Undefined Opcodes Crossing a Segment Limit May Result in
#UD Instead of #GP Exception
Processor may take a #UD (Invalid Opcode) exception instead of a #GP
Problem:
(General Protection) exception when certain undefined opcodes (opcodes 0F
01 D0 - 0F 01 D5) extend beyond the segment limit.
Implication: Due to this erratum, processor may not take a #GP exception in
this situation.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ49. Indication of A20M Support is Inverted
The value read back from VLW_CAPABILITY MSR (1F0H) bit [1] (A20M
Problem:
support) is inverted. Therefore, reading back a '1' (which should indicate
A20M is supported) actually indicates A20M is not supported, and vice versa.
Implication: Software relying on this bit to determine whether A20M feature
is supported by the processor will read back the opposite value of what is
supported.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ50. Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the
Problem:
processor uses to access the VMCS and data structures referenced by pointers
in the VMCS. Due to this erratum, a VMX access to the VMCS or referenced
®
Intel Core™ i7 processor
Specification Update
35