Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 36

data structures will instead use the memory type that the MTRRs (memory-
type range registers) specify for the physical address of the access.
Implication: Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB
(write-back) memory type will be used but the processor may use a different
memory type.
Workaround: Software should ensure that the VMCS and referenced data structures are
located at physical addresses that are mapped to WB memory type by the
MTRRs.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ51. After VM Entry, Instructions May Incorrectly Operate as if CS.D=0
If bit 13 (L) and bit 14 (D/B) of the guest CS access rights field in the VMCS
Problem:
are both 1 and VM entry takes the processor out of IA-32e mode, instructions
executed after VM entry may operate as if CS.D=0.
Implication: Instructions executed after VM entry may use the wrong
operation size. Intel has not observed this erratum with any commercially
available system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ52. Spurious Machine Check Error May Occur When Logical Processor is
Woken Up
The first time a logical processor is woken up after power on (including
Problem:
resume from system sleep states) an Internal Parity Error may be detected
and logged when no real parity error occured.
Implication: When this erratum occurs, a spurious Internal Parity Error may
be logged. However, no machine check exception will be signaled in this case.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ53. B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly
Set
Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6
Problem:
may be incorrectly set for non-enabled breakpoints when the following
sequence happens:
1. MOV or POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist
3. Another instruction after the FP instruction completes successfully
Errata
®
Intel Core™ i7 processor
Specification Update