Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 11

Summary Tables of Changes
No C-0 D-0
AAJ24
X X
AAJ25
X X
AAJ26
X X
AAJ27
X X
AAJ28
X X
AAJ29
X X
AAJ30
X X
AAJ31
X X
AAJ32
X
AAJ33
X X
AAJ34
X X
AAJ35
X X
AAJ36
X
AAJ37
X X
AAJ38
X
AAJ39
X X
AAJ40
X X
AAJ41
X
AAJ42
X
AAJ43
X
AAJ44
X
AAJ45
X X
AAJ46
X X
®
Intel Core™ i7 processor
Specification Update
Status
#GP on Segment Selector Descriptor that Straddles Canonical Boundary
No Fix
May Not Provide Correct Exception Error Code
Improper Parity Error Signaled in the IQ Following Reset When a Code
No Fix
Breakpoint is Set on a #GP Instruction
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV
SS/POP SS Instruction if it is Followed by an Instruction That Signals a
No Fix
Floating Point Exception
IA32_MPERF Counter Stops Counting During On-Demand TM1
No Fix
Intel® QuickPath Memory Controller tTHROT_OPREF Timings May be
No Fix
Violated During Self Refresh Entry
Processor May Over Count Correctable Cache MESI State Errors
No Fix
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow
No Fix
Does Not Work
Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May
No Fix
Result in Stuck Core Operating Ratio
The PECI Throttling Counter May Not be Accurate
Fixed
PECI Does Not Support PCI Configuration Reads/Writes to Misaligned
No Fix
Addresses
OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal
No Fix
Error
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
No Fix
Cause an Unexpected Interrupt
A Processor Core May Not Wake Up from S1 State
Fixed
Reading Reserved APIC Registers May Not Signal an APIC Error
No Fix
A Logical Processor Receiving a SIPI After a VM Entry Into WFS State May
Fixed
Become Unresponsive
Memory Controller May Deliver Incorrect Data When Memory Ranks Are In
No Fix
Power-Down
Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
No Fix
A Floating-Point Store Instruction May Cause an Unexpected x87 FPU
Fixed
Floating-Point Error (#MF)
Incorrect TLB Translation May Occur After Exit From C6
Fixed
USB 1.1 ISOCH Audio Glitches with Intel® QuickPath Interconnect Locks
Fixed
and Deep C-States
Stack Pointer May Become Incorrect In Loops With Unbalanced Push and
Fixed
Pop Operations
A P-state Change While Another Core is in C6 May Prevent Further C-state
No Fix
and P-state Transitions
Certain Store Parity Errors May Not Log Correct Address in
No Fix
IA32_MCi_ADDR
ERRATA
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