Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 42

• Software modifies the paging structures so that there is no valid translation for
the page (e.g., by clearing to 0 the present bit in one of the paging-structure
entries used to translate the page).
• Software later modifies the paging structures so that the translation is again a
valid translation for the page (e.g., by setting to 1 the bit that was cleared
earlier).
• A subsequent instruction loads from a linear address on the page.
• Software did not invalidate TLB entries for the page between the first modification
of the paging structures and the load from the linear address.
In this case, the load bye the later instruction may cause a page fault that indicates
that there is no translation for the page.
Implication: Software may see an unexpected page fault that indicates that
there is no translation for the page.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ70. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
Interrupt is Received while All Cores in C6
If all logical processors in a core are in C6, an ExtINT delivery mode interrupt
Problem:
is pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the
interrupt will be processed after C6 wakeup and after interrupts are re-
enabled (EFLAGS.IF=1). However, the pending interrupt event will not be
cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on
the core servicing the external interrupt. Intel has not observed this erratum
with any commercially available software/system.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ71. Two xAPIC Timer Event Interrupts May Unexpectedly Occur
If an xAPIC timer event is enabled and while counting down the current count
Problem:
reaches 1 at the same time that the processor thread begins a transition to a
low power C-state, the xAPIC may generate two interrupts instead of the
expected one when the processor returns to C0.
Implication: Due to this erratum, two interrupts may unexpectedly be
generated by an xAPIC timer event.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
Errata
®
Intel Core™ i7 processor
Specification Update