Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 61

Errata
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12]
= '1)
Implication: When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows.
Workaround: Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR
(1D9H) bit [12].
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ126. VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a
Problem:
32-bit operand, bit 11 of the VM-exit instruction information field should be
set to 1. Due to this erratum, this bit is instead cleared to 0 (indicating a 16-
bit operand).
Implication: Virtual-machine monitors cannot rely on bit 11 of the VM-exit instruction
information field to determine the operand size of the instruction causing the
VM exit.
Workaround: Virtual-machine monitor software may decode the instruction to determine
operand size.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ127. Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
Performance Monitor Events STORE_BLOCKS.NOT_STA and
Problem:
STORE_BLOCKS.STA should only increment the count when a load is blocked
by a store. Due to this erratum, the count will be incremented whenever a
load hits a store, whether it is blocked or can forward. In addition this event
does not count for specific threads correctly.
Implication: If Intel® Hyper-Threading Technology is disabled, the Performance
Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may
indicate a higher occurrence of loads blocked by stores than have actually
occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads
blocked by stores may be unpredictable and they could be higher or lower
than the correct count.
Implication: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ128. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
®
Intel Core™ i7 processor
Specification Update
61