Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 45

Errata
written (as part of the write-read ESR access flow). The corresponding error
interrupt will also not be generated for this case.
Implication: Due to this erratum, an incoming illegal vector error may not be
logged into ESR properly and may not generate an error interrupt.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ79. CPUID Incorrectly Indicates the UnHalted Reference Cycle
Architectural Event is Supported
The architectural performance monitoring event for UnHalted Reference
Problem:
Cycles (3CH, Umask 01H) is not supported on the processor. The CPUID
instruction, when executed with EAX = 0AH, should return bit 2 of EBX as 1 to
indicate that this event is not supported. Due to this erratum, CPUID will
improperly return bit 2 as 0.
Implication: Software relying on the CPUID instruction to determine support
of the UnHalted Reference Cycles event will incorrectly assume the event is
available.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ80. Architectural Performance Monitor Event 'Branch Misses Retired' is
Counted Incorrectly
The Architectural Performance Monitor Event 'branch misses retired' (Event
Problem:
C5H) is not counted correctly and may result in an under count or an over
count.
Implication: The Architectural Performance Monitor Event 'branch misses
retired' will not show accurate results when counted.
Workaround: It is possible for the BIOS to contain a workaround for this erratum which
reports via CPUID that this event is not available.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ81. DR6 May Contain Incorrect Information When the First Instruction
After a MOV SS,r/m or POP SS is a Store
Normally, each instruction clears the changes in DR6 (Debug Status Register)
Problem:
caused by the previous instruction. However, the instruction following a MOV
SS,r/m (MOV to the stack segment selector) or POP SS (POP stack segment
selector) instruction will not clear the changes in DR6 because data
breakpoints are not taken immediately after a MOV SS,r/m or POP SS
®
Intel Core™ i7 processor
Specification Update
45