No
C-0
D-0
AAJ1
X
X
AAJ2
X
X
AAJ3
X
X
AAJ4
X
X
AAJ5
X
X
AAJ6
X
X
AAJ7
X
X
AAJ8
X
X
AAJ9
X
X
AAJ10
X
X
AAJ11
X
X
AAJ12
X
X
AAJ13
X
X
AAJ14
X
X
AAJ15
X
X
AAJ16
X
X
AAJ17
X
X
AAJ18
X
X
AAJ19
X
X
AAJ20
X
X
AAJ21
X
X
AAJ22
X
X
AAJ23
X
X
Status
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a
No Fix
DTLB Error
Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
No Fix
Breakpoints
MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
No Fix
Corruption of CS Segment Register During RSM While Transitioning From
No Fix
Real Mode to Protected Mode
The Processor May Report a #TS Instead of a #GP Fault
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data
No Fix
Size or Lead to Memory-Ordering Violations
Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions and May Push the Wrong Address
No Fix
Onto the Stack
Performance Monitor SSE Retired Instructions May Return Incorrect Values
No Fix
Premature Execution of a Load Operation Prior to Exception Handler
No Fix
Invocation
MOV To/From Debug Registers Causes Debug Exception
No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image
No Fix
Leads to Partial Memory Update
Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
No Fix
Single Step Interrupts with Floating Point Exception Pending May Be
No Fix
Mishandled
Fault on ENTER Instruction May Result in Unexpected Values on Stack
No Fix
Frame
IRET under Certain Conditions May Cause an Unexpected Alignment Check
No Fix
Exception
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May
No Fix
be Preempted
General Protection (#GP) Fault May Not Be Signaled on Data Segment
No Fix
Limit Violation above 4-G Limit
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt
No Fix
Occurs in 64-bit Mode
Performance Monitoring Events for Read Miss to Level 3 Cache Fill
No Fix
Occupancy Counter may be Incorrect
A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as
No Fix
Armed
Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
No Fix
Delivery Status of the LINT0 Register of the Local Vector Table May be Lost
No Fix
Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
No Fix
Summary Tables of Changes
ERRATA
®
Intel
Core™ i7 processor
Specification Update
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