Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 32

AAJ37. Reading Reserved APIC Registers May Not Signal an APIC Error
Reads of reserved APIC registers in xAPIC compatibility mode should signal
Problem:
an APIC error with the Illegal Register Address bit [11] set in the Error Status
Register (offset 0x280). Due to the erratum, the error is neither logged nor
signaled.
Implication: A reserved APIC register access error interrupt may not be
logged or signaled, even though the APIC error interrupt is enabled, on a read
of a reserved APIC register.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ38. A Logical Processor Receiving a SIPI After a VM Entry Into WFS State
May Become Unresponsive
A logical processor may become unresponsive after receiving a SIPI (Start-up
Problem:
Interprocessor Interrupt) following a VM Entry into a WFS (Wait-for-SIPI)
state.
Implication: The logical processor that receives a SIPI while in the WFS state
may stop responding.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ39. Memory Controller May Deliver Incorrect Data When Memory Ranks
Are In Power-Down
When one or more memory ranks are in Power-Down (as controlled by
Problem:
MC_CHANNEL_{0,1,2}_CKE_TIMING CSR parameters), certain memory
access patterns may result in incorrect data.
Implication: Due this erratum, incorrect data may result.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ40. Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
Under a specific set of conditions, MMX stores (MOVD, MOVQ, MOVNTQ,
Problem:
MASKMOVQ) which cause memory access faults (#GP, #SS, #PF, or #AC),
may incorrectly update the x87 FPU tag word register.
This erratum will occur when the following additional conditions are also met.
Errata
®
Intel Core™ i7 processor
Specification Update