Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 57

Errata
AAJ114. Uncacheable Access to a Monitored Address Range May Prevent
Future Triggering of the Monitor Hardware
It is possible that an address range which is being monitored via the
Problem:
MONITOR instruction could be written without triggering the monitor
hardware. A read from the monitored address range which is issued as
uncacheable (for example having the CR0.CD bit set) may prevent
subsequent writes from triggering the monitor hardware. A write to the
monitored address range which is issued as uncacheable, may not trigger the
monitor hardware and may prevent subsequent writes from triggering the
monitor hardware.
Implication: The MWAIT instruction will not exit the optimized power state and resume
program flow if the monitor hardware is not triggered.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ115. BIST Results May be Additionally Reported After a GETSEC[WAKEUP]
or INIT-SIPI Sequence
BIST results should only be reported in EAX the first time a logical processor
Problem:
wakes up from the Wait-For-SIPI state. Due to this erratum, BIST results may
be additionally reported after INIT-SIPI sequences and when waking up RLP's
from the SENTER sleep state using the GETSEC[WAKEUP] command.
Implication: An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when
a zero value is expected. RLP's waking up for the SENTER sleep state using
the GETSEC[WAKEUP] command may show a different value in EAX upon
wakeup than before going into the SENTER sleep state.
Workaround: If necessary software may save the value in EAX prior to launching into the
secure environment and restore upon wakeup and/or clear EAX after the
INIT-SIPI sequence.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ116. Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
x87 instructions that trigger #MF normally service interrupts before the #MF.
Problem:
Due to this erratum, if an instruction that triggers #MF is executed while
Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost
Technology transitions, or Thermal Monitor events occur, the pending #MF
may be signaled before pending interrupts are serviced.
Implication: Software may observe #MF being signaled before pending interrupts are
serviced.
Workaround: None identified.
®
Intel Core™ i7 processor
Specification Update
57