Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 37

Errata
4. A breakpoint occurs due to either a data breakpoint on the preceding instruction
or a code breakpoint on the next instruction.
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2 may be
reported in B0-B3 after the breakpoint occurs in step 4.
Implication: Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for
non-enabled breakpoints.
Workaround: Software should not execute a floating point instruction directly after a MOV
SS or POP SS instruction.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ54. Core C6 May Clear Previously Logged TLB Errors
Following an exit from core C6, previously logged TLB (Translation Lookaside
Problem:
Buffer) errors in IA32_MCi_STATUS may be cleared.
Implication: Due to this erratum, TLB errors logged in the associated machine
check bank prior to core C6 entry may be cleared. Provided machine check
exceptions are enabled, the machine check exception handler can log any
uncorrectable TLB errors prior to core C6 entry. The TLB marks all detected
errors as uncorrectable.
Workaround: As long as machine check exceptions are enabled, the machine check
exception handler can log the TLB error prior to core C6 entry. This will
ensure the error is logged before it is cleared.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ55. Processor May Hang When Two Logical Processors Are in Specific Low
Power States
When two logical processors in a physical core have entered the C1 and C6
Problem:
idle states respectively, it is possible that the processor may hang and log a
machine check error with IA32_MCi_STATUS.MCACOD = 0x0106. The error
does not occur when either core has entered C3 or when both logical
processors enter the same idle state.
Implication: Due to this erratum, a hang may occur and a machine check
may be logged while two logical processors are in a low power state.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ56. MOVNTDQA From WC Memory May Pass Earlier Locked Instructions
An execution of MOVNTDQA that loads from WC (write combining) memory
Problem:
may appear to pass an earlier locked instruction to a different cache line.
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Intel Core™ i7 processor
Specification Update
37