Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 12

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Status
xAPIC Timer May Decrement Too Quickly Following an Automatic Reload
No Fix
While in Periodic Mode
Certain Undefined Opcodes Crossing a Segment Limit May Result in #UD
No Fix
Instead of #GP Exception
Indication of A20M Support is Inverted
No Fix
Reported Memory Type May Not Be Used to Access the VMCS and
No Fix
Referenced Data Structures
After VM Entry, Instructions May Incorrectly Operate as if CS.D=0
Fixed
Spurious Machine Check Error May Occur When Logical Processor is Woken
Fixed
Up
B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
No Fix
Core C6 May Clear Previously Logged TLB Errors
No Fix
Processor May Hang When Two Logical Processors Are in Specific Low
No Fix
Power States
MOVNTDQA From WC Memory May Pass Earlier Locked Instructions
No Fix
Performance Monitor Event MISALIGN_MEM_REF May Over Count
No Fix
Changing the Memory Type for an In-Use Page Translation May Lead to
No Fix
Memory-Ordering Violations
Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB
Fixed
Translation
The "Virtualize APIC Accesses" VM-Execution Control May be Ignored
Fixed
C6 Transitions May Cause Spurious Updates to the xAPIC Error Status
Fixed
Register
Critical ISOCH Traffic May Cause Unpredictable System Behavior When
Fixed
Write Major Mode Enabled
Running with Write Major Mode Disabled May Lead to a System Hang
No Fix
Memory Controller Address Parity Error Injection Does Not Work Correctly
No Fix
Memory Controller Opportunistic Refreshes Might be Missed
No Fix
Delivery of Certain Events Immediately Following a VM Exit May Push a
No Fix
Corrupted RIP Onto The Stack
The Combination of a Bus Lock and a Data Access That is Split Across Page
No Fix
Boundaries May Lead to Processor Livelock
CPUID Instruction Returns Incorrect Brand String
No Fix
An Unexpected Page Fault May Occur Following the Unmapping and Re-
No Fix
mapping of a Page
Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
No Fix
Interrupt is Received while All Cores in C6
Two xAPIC Timer Event Interrupts May Unexpectedly Occur
No Fix
Summary Tables of Changes
ERRATA
®
Intel Core™ i7 processor
Specification Update