Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 33

Errata
• The MMX store instruction must be the first MMX instruction to operate on x87 FPU
state (i.e. the x87 FP tag word is not already set to 0x0000).
• For MOVD, MOVQ, MOVNTQ stores, the instruction must use an addressing mode
that uses an index register (this condition does not apply to MASKMOVQ).
Implication: If the erratum conditions are met, the x87 FPU tag word register
may be incorrectly set to a 0x0000 value when it should not have been
modified.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ41. A Floating-Point Store Instruction May Cause an Unexpected x87 FPU
Floating-Point Error (#MF)
If a floating-point store instruction (FST or FSTP) causes an inexact-result
Problem:
exception (#P) and such exceptions are unmasked, the next "waiting" x87
FPU instruction or WAIT/FWAIT instruction will incur an x87 FPU Floating-
Point Error (#MF). Due to this erratum, the #MF may occur prematurely and
prevent the floating-point store instruction from executing. This may occur
when the logical processor is in VMX non-root operation and either (1) the
"use EPT" VM-execution control is 1; or (2) the "virtual APIC accesses" VM-
execution control is 1 and the store is to the APIC-access page.
Implication: Due to this erratum, a floating-point store instruction may cause
a #MF that should be held pending until the next "waiting" x87 FPU
instruction or WAIT/FWAIT instruction.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ42. Incorrect TLB Translation May Occur After Exit From C6
Under certain conditions when C6 and two logical processors on the same
Problem:
core are enabled on a processor, an instruction fetch occurring after a logical
processor exits from C6 may incorrectly use the translation lookaside buffer
(TLB) address mapping belonging to the other logical processor in the
processor core.
Implication: When this erratum occurs, unpredictable behavior may result.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ43. USB 1.1 ISOCH Audio Glitches with Intel® QuickPath Interconnect
Locks and Deep C-States
®
Intel Core™ i7 processor
Specification Update
33