Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 55

Errata
Implication: The performance monitor event INSTR_RETIRED and
MEM_INST_RETIRED may reflect a count lower than the actual number of
events.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AAJ108. A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7)
Problem:
is reserved in PML4Es and PDPTEs. If the translation of the linear address of a
memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault
should occur. Due to this erratum, PS of such an entry is ignored and no page
fault will occur due to its being set.
Implication: Software may not operate properly if it relies on the processor to
deliver page faults when reserved bits are set in paging-structure entries.
Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit
0) set to "1".
For the steppings affected, see the Summary Tables of Changes.
Status:
AAJ109. tRP Timing Violations May be Observed Near a Self Refresh Entry
When entering package C3, C6 or S3 states, tRP violations may be observed
Problem:
near a self refresh (that is part of the C3, C6 or S3 entry).
Implication: tRP timing violation may occur on DRAM entry to self refresh while entering
package C3, C6 or S3 states. Intel has not observed this erratum with any
commercially available software. This condition has only been produced in
simulation and affects a pre-charge to banks already pre-charged.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ110. System May Hang if
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL
Commands Are Not Issued in Increasing Populated DDR3 Rank Order
ZQCL commands are used during initialization to calibrate DDR3
Problem:
termination. A ZQCL command can be issued by writing 1 to the
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL (Device 4,5,6,
Function 0, Offset 15, bit[15]) field and it targets the DDR3 rank specified in
the RANK field (bits[7:5]) of the same register. If the ZQCL commands are
not issued in increasing populated rank order then ZQ calibration may not
complete, causing the system to hang.
®
Intel Core™ i7 processor
Specification Update
55