Errata - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Specification

Errata

AJ1. Deleted
Status:
AJ2. LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is
received during a snoop phase and the Locked transaction is pipelined on the front side
bus (FSB), LOCK# may unexpectedly de-assert.
Implication: When this erratum occurs, the system may hang during shutdown. Intel has not
observed this erratum with any commercially available systems or software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ3. Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in
the MCA address register (MCi_ADDR). Under some scenarios, the address reported
may be incorrect.
Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
errors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ4. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF)
is zero after executing the following instructions
1) VERR (ZF=0 indicates unsuccessful segment read verification)
2) VERW (ZF=0 indicates unsuccessful segment write verification)
3) LAR (ZF=0 indicates unsuccessful access rights load)
4) LSL (ZF=0 indicates unsuccessful segment limit load)
Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR instructions are
executed after the occurrence of an exception.
Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR
before executing VERW/VERR/LSL/LAR instructions.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ5. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Problem: Performance monitoring for Event CFH normally increments on saturating SIMD
instruction retired. Regardless of DR7 programming, if the linear address of a retiring
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.
18 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010