Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 21

Errata
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type
to UC, WP or WT memory type within a single REP MOVS or REP STOS
instruction that will execute with fast strings enabled.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ7. Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions and May Push the Wrong
Address Onto the Stack
Normally, when the processor encounters a Segment Limit or Canonical Fault
Problem:
due to code execution, a #GP (General Protection Exception) fault is
generated after all higher priority Interrupts and exceptions are serviced. Due
to this erratum, if RSM (Resume from System Management Mode) returns to
execution flow that results in a Code Segment Limit or Canonical Fault, the
#GP fault may be serviced before a higher priority Interrupt or Exception (e.g.
NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC),
etc.). If the RSM attempts to return to a non-canonical address, the address
pushed onto the stack for this #GP fault may not match the non-canonical
address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced
before higher priority Interrupts and Exceptions. Intel has not observed this
erratum on any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ8. Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to
Problem:
track retired SSE instructions. Due to this erratum, the processor may also
count other types of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may
report count higher than expected.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
®
Intel Core™ i7 processor
Specification Update
21