Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 22

AAJ9. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
If any of the below circumstances occur, it is possible that the load portion of
Problem:
the instruction will have executed before the exception handler is entered.
• If an instruction that performs a memory load causes a code segment limit
violation.
• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point
Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication: In normal code execution where the target of the load operation
is to write back memory there is no impact from the load being prematurely
executed, or from the restart and subsequent re-execution of that instruction
by the exception handler. If the target of the load is to uncached memory that
has a system side-effect, restarting the instruction may cause unexpected
system behavior due to the repetition of the side-effect. Particularly, while
CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may
issue a memory load before getting the DNA exception.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions
when accessing side-effect memory and by ensuring that all code is written
such that a code segment limit violation cannot occur as a part of reading
from side-effect memory.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ10. MOV To/From Debug Registers Causes Debug Exception
When in V86 mode, if a MOV instruction is executed to/from a debug
Problem:
registers, a general-protection exception (#GP) should be generated.
However, in the case when the general detect enable flag (GD) bit is set, the
observed behavior is that a debug exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set),
when attempting to execute a MOV on debug registers in V86 mode, a debug
exception will be generated instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86
mode. The GD bit is generally set and used by debuggers. The debug
exception handler should check that the exception did not occur in V86 mode
before continuing. If the exception did occur in V86 mode, the exception may
be directed to the general-protection exception handler.
For the steppings affected, see the Summary Table of Changes.
Status:
Errata
®
Intel Core™ i7 processor
Specification Update