Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 62

When a performance monitoring counter is configured for PEBS (Precise Event
Problem:
Based Sampling), overflow of the counter results in storage of a PEBS record
in the PEBS buffer. The information in the PEBS record represents the state
of the next instruction to be executed following the counter overflow. Due to
this erratum, if the counter overflow occurs after execution of either MOV SS
or STI, storage of the PEBS record is delayed by one instruction..
Implication: When this erratum occurs, software may observe storage of the PEBS record
being delayed by one instruction following execution of MOV SS or STI. The
state information in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ129. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask
Problem:
01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions.
Due to this erratum, if only a small number of MMX instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX
may be lower than expected. The degree of undercounting is dependent on
the occurrences of the erratum condition while the counter is active. Intel has
not observed this erratum with any commercially available software.
Workaround: None Identified.
For the steppings affected, see the Summary Table of Changes
Status:
AAJ130. INVLPG Following INVEPT or INVVPID May Fail to Flush All
Translations for a Large Page
This erratum applies if the address of the memory operand of an INVEPT or
Problem:
INVVPID instruction resides on a page larger than 4KBytes and either (1) that
page includes the low 1 MBytes of physical memory; or (2) the physical
address of the memory operand matches an MTRR that covers less than 4
MBytes. A subsequent execution of INVLPG that targets the large page and
that occurs before the next VM-entry instruction may fail to flush all TLB
entries for the page. Such entries may persist in the TLB until the next VM-
entry instruction.
Implication: Accesses to the large page between INVLPG and the next VM-entry instruction
may incorrectly use translations that are inconsistent with the in-memory
page tables
Workaround: None Identified.
Errata
®
Intel Core™ i7 processor
Specification Update