Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 47

Errata
enable bit in the corresponding performance monitor event select MSR. For
the usage model where no counting is desired, program that Uncore general
performance counter's global enable bit to be zero.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ85. Processors with SMT May Hang on P-State Transition or ACPI Clock
Modulation Throttling
When SMT is enabled, it is possible that a P-state transition or ACPI clock
Problem:
modulation throttling may hang and log a machine check error with
IA32_MCi_STATUS.MCACOD = 0x0150. This hang condition requires a
specific sequence of instructions coincident with the P-state or ACPI event.
Implication: When this erratum occurs, the processor will unexpectedly hang.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ86. Performance Monitor Counter INST_RETIRED.STORES May Count
Higher than Expected
Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used
Problem:
to track retired instructions which contain a store operation. Due to this
erratum, the processor may also count other types of instructions including
WRMSR and MFENCE.
Implication: Performance Monitoring counter INST_RETIRED.STORES may
report counts higher than expected.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ87. Sleeping Cores May Not be Woken Up on Logical Cluster Mode
Broadcast IPI Using Destination Field Instead of Shorthand
If software sends a logical cluster broadcast IPI using a destination shorthand
Problem:
of 00B (No Shorthand) and writes the cluster portion of the Destination Field
of the Interrupt Command Register to all ones while not using all 1s in the
mask portion of the Destination Field, target cores in a sleep state that are
identified by the mask portion of the Destination Field may not be woken up.
This erratum does not occur if the destination shorthand is set to 10B (All
Including Self) or 11B (All Excluding Self).
Implication: When this erratum occurs, cores which are in a sleep state may
not wake up to handle the broadcast IPI. Intel has not observed this erratum
with any commercially available software.
®
Intel Core™ i7 processor
Specification Update
47