Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 15

Summary Tables of Changes
No C-0 D-0
AAJ117
X X
AAJ118
X X
AAJ119
X X
AAJ120
X X
AAJ121
X X
AAJ122
X X
AAJ123
X X
AAJ124
X X
AAJ125
X X
AAJ126
X X
AAJ127
X
AAJ128
X X
AAJ129
X X
AAJ130
X X
AAJ131
X X
AAJ132
X X
AAJ133
X X
AAJ134
X X
AAJ135
X X
AAJ136
X X
AAJ137
X X
AAJ138
X X
AAJ139
X X
®
Intel Core™ i7 processor
Specification Update
Status
VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
No Fix
VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET
No Fix
NMI Blocking
Multiple Performance Monitor Interrupts are Possible on Overflow of
No Fix
IA32_FIXED_CTR2
LBRs May Not be Initialized During Power-On Reset of the Processor
No Fix
Unexpected Interrupts May Occur on C6 Exit If Using APIC Timer to
No Fix
Generate Interrupts
LBR, BTM or BTS Records May have Incorrect Branch From
Information After an EIST Transition, T-states, C1E, or Adaptive Thermal
No Fix
Throttling
Redirection to Probe Mode May be delayed beyond Intended Instruction
No Fix
VMX-Preemption Timer Does Not Count Down at the Rate Specified
No Fix
Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed
No Fix
Counter 0
VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Operand Size
No Fix
Performance Monitoring Events STORE_BLOCKS.NOT_STA and
No Fix
STORE_BLOCKS.STA May Not Count Events Correctly
Storage of PEBS Record Delayed Following Execution of MOV SS or STI
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count
No Fix
Some Transitions
INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for
Plan Fix
a Large Page
The PECI Bus May be Tri-stated After System Reset
No Fix
LER MSRs May Be Unreliable
No Fix
An Exit From the Core C6-state May Result in the Dropping of an Interrupt
No Fix
PMIs During Core C6 Transitions May Cause the System to Hang
No Fix
2MB Page Split Lock Accesses Combined With Complex Internal Events
No Fix
May Cause Unpredictable System Behavior
IA32_MC8_CTL2 MSR is Not Cleared on Processor Warm Reset
No Fix
The Combination of a Page-Split Lock Access And Data Accesses That Are
No Fix
Split Across Cacheline Boundaries May Lead to Processor Livelock
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access
Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in
No Fix
64-bit Mode
IO_SMI Indication in SMRAM State Save Area May Be Lost
No Fix
ERRATA
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