Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 25

Errata
Implication: Software may observe a lower-priority fault occurring before or
in lieu of a #GP fault. Instructions of greater than 15 bytes in length can only
occur if redundant prefixes are placed before the instruction.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ17. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
In 32-bit mode, memory accesses to flat data segments (base = 00000000h)
Problem:
that occur above the 4G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system
may not issue a #GP fault.
Workaround: Software should ensure that memory accesses in 32-bit mode do not occur
above the 4G limit (0ffffffffh).
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ18. LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
An exception/interrupt event should be transparent to the LBR (Last Branch
Problem:
Record), BTS (Branch Trace Store) and BTM (Branch Trace Message)
mechanisms. However, during a specific boundary condition where the
exception/interrupt occurs right after the execution of an instruction at the
lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR
return registers will save a wrong return address with bits 63 to 48 incorrectly
sign extended to all 1's. Subsequent BTS and BTM operations which report
the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event
of an exception/interrupt.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ19. Performance Monitoring Events for Read Miss to Level 3 Cache Fill
Occupancy Counter may be Incorrect
Whenever an Level 3 cache fill conflicts with another request's address, the
Problem:
miss to fill occupancy counter, UNC_GQ_ALLOC.RT_LLC_MISS (Event 02H),
will provide erroneous results.
Implication: The Performance Monitoring UNC_GQ_ALLOC.RT_LLC_MISS
event may count a value higher than expected. The extent to which the value
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Intel Core™ i7 processor
Specification Update
25