Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 51

Errata
is restarted because the instruction will produce the same results as if it had
initially completed without fault or VM exit.
Workaround: If the handler of the affected events inspects the arithmetic portion of the
saved EFLAGS value, then system software should perform a synchronized
paging structure modification and TLB invalidation.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ97. System May Hang if
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL Commands
Are Not Issued in Increasing Populated DDR3 Rank Order
ZQCL commands are used during initialization to calibrate DDR3 termination.
Problem:
A ZQCL command can be issued by writing 1 to the
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL (Device 4,5,6,
Function 0, Offset 15, bit[15]) field and it targets the DDR3 rank specified in
the RANK field (bits[7:5]) of the same register. If the ZQCL commands are
not issued in increasing populated rank order then ZQ calibration may not
complete, causing the system to hang.
Implication: Due to this erratum the system may hang if writes to the
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL field are not in
increasing populated DDR3 rank order.
Workaround: It is possible for Intel provided BIOS reference code to contain a workaround
for this erratum. Please refer to the latest version of BIOS Memory Reference
Code and release notes.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ98. LER and LBR MSRs May Be Incorrectly Updated During a Task Switch
LER (Last Exception Record) and LBR (Last Brand Record) MSRs
Problem:
(MSR_LER_FROM_LIP (1DDH), MSR_LER_TO_LIP (1DEH) and
MSR_LASTBRANCH{0:15}_FROM_IP (680H – 68FH)) may contain incorrect
values after a fault or trap that does a task switch.
Implication: After a task switch the value of the LER and LBR MSRs may be
updated to point to incorrect instructions.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ99. Virtualized WRMSR to the IA32_EXT_XAPIC_TPR MSR Uses Incorrect
Value for TPR Threshold
®
Intel Core™ i7 processor
Specification Update
51