Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 31

Errata
Workaround: PECI host controllers may issue byte, word and Dword reads and writes as
long as they are aligned to Dword addresses.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ34. OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific
lnternal Error
If a specific type of internal unclassified error is detected, as identified by
Problem:
IA32_MCi_STATUS.MCACOD=0x0405, the IA32_MCi_ STATUS.OVER
(overflow) bit [62] may be erroneously set.
Implication: The OVER bit of the MCi_STATUS register may be incorrectly set
for a specific internal unclassified error.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ35. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
If a local interrupt is pending when the LVT entry is written, an interrupt may
Problem:
be taken on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector
when a LVT entry is written, even if the new LVT entry has the mask bit set.
If there is no Interrupt Service Routine (ISR) set up for that vector the system
will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the
vector will be left set in the in-service register and mask all interrupts at the
same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with
it, even if that vector was programmed as masked. This ISR routine must do
an EOI to clear any unexpected interrupts that may occur. The ISR associated
with the spurious vector does not generate an EOI, therefore the spurious
vector should not be used when writing the LVT.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ36. A Processor Core May Not Wake Up from S1 State
If there is an interrupt pended at the same time as the package is entering S1
Problem:
and one of the cores in the package is entering C3, it is possible that the core
entering C3 may not wake up from the S1 state.
Implication: Due to this erratum, the processor core may not wake up from
S1 state.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
®
Intel Core™ i7 processor
Specification Update
31