Intel CORE I7-900 DEKSTOP - SPECIFICATION Specification page 50

AAJ94. Processor May Incorrectly Demote Processor C6 State to a C3 State
The auto demotion feature on the processor demotes processor C6 C-state
Problem:
requests to C3 in a more aggressive manner than expected, leading to low C6
residency.
Implication: Due to this erratum, the system may exhibit higher than
expected idle power due to low C6 residency.
Workaround: It possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ95. Performance Monitor Event Offcore_response_0 (B7H) Does Not
Count NT Stores to Local DRAM Correctly
When a IA32_PERFEVTSELx MSR is programmed to count the
Problem:
Offcore_response_0 event (Event:B7H), selections in the OFFCORE_RSP_0
MSR (1A6H) determine what is counted. The following two selections do not
provide accurate counts when counting NT (Non-Temporal) Stores:
- OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
- OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is set
to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have been.
Implication: The counter for the Offcore_response_0 event may be incorrect
for NT stores.
Workaround: None identified.
For the steppings affected, see the Summary Table of Changes.
Status:
AAJ96. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
This erratum is regarding the case where paging structures are modified to
Problem:
change a linear address from writable to non-writable without software
performing an appropriate TLB invalidation. When a subsequent access to
that address by a specific instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG,
DEC, INC, NEG, NOT, OR, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB,
XOR, and XADD) causes a page fault or an EPT-induced VM exit, the value
saved for EFLAGS may incorrectly contain the arithmetic flag values that the
EFLAGS register would have held had the instruction completed without fault
or VM exit. For page faults, this can occur even if the fault causes a VM exit or
if its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved by an affected
event (a page fault or an EPT-induced VM exit) may contain incorrect
arithmetic flag values, Intel has not identified software that is affected by this
erratum. This erratum will have no further effects once the original instruction
Errata
®
Intel Core™ i7 processor
Specification Update