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Table 7-8.
DDR3 Signal Group DC Specifications
Symbol
Parameter
V
Input Low Voltage
IL
V
Input High Voltage
IH
V
Output Low Voltage
OL
V
Output High Voltage
OH
R
DDR3 Clock Buffer On
ON
Resistance
R
DDR3 Command Buffer On
ON
Resistance
R
DDR3 Control Buffer On
ON
Resistance
R
DDR3 Data Buffer On
ON
Resistance
On-Die Termination for
Data ODT
Data Signals
I
Input Leakage Current
LI
COMP Resistance
SM_RCOMP0
COMP Resistance
SM_RCOMP1
COMP Resistance
SM_RCOMP2
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
IL
3.
V
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
IH
4.
V
and V
may experience excursions above V
IH
OH
specifications.
5.
This is the pull down driver resistance.
6.
R
is the termination on the DIMM and is not controlled by the processor.
VTT_TERM
7.
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V
74
Alpha
Min
Group
(e,f)
—
(e,f)
0.57*V
DDQ
(V
(c,d,e,f)
—
(R
V
(c,d,e,f)
—
(R
ON
—
21
—
20
—
20
—
21
(d)
93.5
—
—
(t)
99
(t)
24.7
(t)
128.7
. However, input signal drivers must comply with the signal quality
DDQ
Electrical Specifications
Typ
Max
—
0.43*V
—
—
/ 2)* (R
/
DDQ
ON
—
+R
))
ON
VTT_TERM
– ((V
/ 2)*
DDQ
DDQ
—
/(R
+R
))
ON
VTT_TERM
—
36
—
31
—
31
—
36
—
126.5
—
± 1
100
101
24.9
25.1
130
131.3
SS
1
Units
Notes
V
2,4
DDQ
V
3
6
V
4,6
5
5
5
5
mA
7
7
7
.
Datasheet, Volume 1
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