Amrc Interrupt Flag Register - Epson S1C17M01 Technical Manual

Bit 5 PSEOUT
This bit indicates the pulse output (EVPLS pin) status.
1 (R): High level output
0 (R): Low level output
Bit 4 CTLEN
This bit indicates the measurement status.
1 (R): Measuring
0 (R): Idle
Bit 3 Reserved
Bits 2–0 PHASE[2:0]
These bits indicate the current phase number.
The correct value may not be read during measurement. The AMRCSTAT.PHASE[2:0] bits must be
read twice and assume the counter value was read successfully if the two read results are the same.

AMRC Interrupt Flag Register

Register name Bit
AMRCINTF 15–13 –
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits 15–13 Reserved
Bit 11 Reserved
Bit 6 Reserved
Bit 4 Reserved
Bit 12 UCNTIF
Bit 10 CNT2IF
Bit 9 CNT1IF
Bit 8 CNT0IF
Bit 7 DIF1IF
Bit 5 DIF0IF
Bit 3 RSKIPIF
Bit 2 STPIF
Bit 1 REVRIF
Bit 0 NMLRIF
These bits indicate the AMRC interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
AMRCINTF.UCNTIF bit: Unit counter compare match interrupt
AMRCINTF.CNT2IF bit: Event counter Ch.2 underflow interrupt
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x0
UCNTIF 0
(reserved) 0
CNT2IF 0
CNT1IF 0
CNT0IF 0
DIF1IF 0
(reserved) 0
DIF0IF 0
(reserved) 0
RSKIPIF 0
STPIF 0
REVRIF 0
NMLRIF 0
Seiko Epson Corporation
16 MR SENSOR CONTROLLER (AMRC)
Reset R/W
– R –
H0 R/W Cleared by writing 1.
H0 R –
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
H0 R/W
H0 R –
H0 R/W Cleared by writing 1.
H0 R –
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
H0 R/W
Remarks
16-13