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REVISION HISTORY
Code No.
Page
412361702
8-2
8.3.2 Theoretical Regulation Function
Corrected Step 1.
1. Measure f
8-4
8.4.2 Real-Time Clock Counter Operations
Corrective operation when a value out of the effective range is set
Added a note.
Note: Do not set the RTCMON.RTCMOL[3:0] bits to 0x0 if the RTCMON.RTCMOH bit = 0.
8-6
8.6 Control Registers
RTC Control Register
Bits 14–8 RTCTRM[6:0]
Added a note.
Notes: ...
8-11
8.6 Control Registers
RTC Month/Day Register
Bit 12
Bits 11–8 RTCMOL[3:0]
Added a note.
Notes: ...
9-3
9.4.1 SVD Control
Starting detection
Corrected Step 4.
4. ...
13-7 to 8
13.4.3 Data Reception in Master Mode
Data receiving procedure
Added Step 1. (The old step numbers were carried down in order.)
1. When receiving one-byte data, write 1 to the I2CnCTL.TXNACK bit.
Modified Figure 13.4.3.2.
A flow for Step 1 was added.
13-12 to 13 13.4.6 Data Reception in Slave Mode
Data receiving procedure
Added Step 1. (The old step numbers were carried down in order.)
1. When receiving one-byte data, write 1 to the I2CnCTL.TXNACK bit.
Modified Figure 13.4.6.2.
A flow for Step 1 was added.
14-2
14.2.1 List of Output Pins
Modified Table 14.2.1.1.
SEGxx/COMxx pin I/O: O → A
14-4
14.4.3 External Voltage Application Mode 2
Corrected the description.
In this mode, the LCD drive voltage V
internally generated.
14-6
14.5.2 Display On/Off
Added a note.
Note: When "Display off" is selected, the electric charges of V
17-1
17.2 Recommended Operating Conditions
Modified the characteristics table.
C
A note (*1) was added.
*1 When the LCD driver is used with V
18-1
18 Basic External Connection Diagram
Modified the figure.
C
19-1
19 Package
A JEITA name was added to the package name.
and calculate the frequency tolerance correction value
OSC1
"m [ppm] = -{(f
- 32,768 [Hz]) / 32,768 [Hz]} × 10
OSC1
(Eq. 8.1) m: OSC1 frequency tolerance correction value [ppm]
• Writing 0x00 to the RTCCTL.RTCTRM[6:0] bits sets the RTCCTL.RTCTRMBSY bit to 1 as well.
However, no correcting operation is performed.
RTCMOH
• Be sure to avoid setting the RTCMON.RTCMOH/RTCMOL[3:0] bits to 0x00.
- Set the SVDINTE.SVDIE bit to 1.
following procedure.
...
To turn the display on again, perform the above procedure in the reverse order.
was Added.
VPP
V
| ≥ 0.4 V.
DD
was added.
VPP
Contents
."
6
or V
is applied from outside the IC and other voltages are
C1
C2
C4
≥ 4.6 V, the LCD power supply voltage should be set as |V
DD
(or V
) must be discharged in the
C3
-
C3
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