Data Format; Operations; Initialization; Data Transmission In Master Mode - Epson S1C17M01 Technical Manual

12.4 Data Format

The SPIA data length can be selected from 2 bits to 16 bits by setting the SPInMOD.CHLN[3:0] bits. The input/
output permutation is configurable to MSB first or LSB first using the SPInMOD.LSBFST bit. Figure 12.4.1 shows
a data format example when the SPInMOD.CHLN[3:0] bits = 0x7, the SPInMOD.CPOL bit = 0 and the SPInMOD.
CPHA bit = 0.
Cycle No.
SPInMOD. SPICLKn
LSBFST bit
SDOn
0
SDIn
SDOn
1
SDIn
Writing Dw[7:0] to the SPInTXD register
Figure 12.4.1 Data Format Selection Using the SPInMOD.LSBFST Bit
(SPInMOD.CHLN[3:0] bits = 0x7, SPInMOD.CPOL bit = 0, SPInMOD.CPHA bit = 0)

12.5 Operations

12.5.1 Initialization

SPIA Ch.n should be initialized with the procedure shown below.
1. <Master mode only> Generate a clock by controlling the 16-bit timer and supply it to SPIA Ch.n.
2. Configure the following SPInMOD register bits:
- SPInMOD.PUEN bit
- SPInMOD.NOCLKDIV bit
- SPInMOD.LSBFST bit
- SPInMOD.CPHA bit
- SPInMOD.CPOL bit
- SPInMOD.MST bit
3. Assign the SPIA Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
4. Set the following SPInCTL register bits:
- Set the SPInCTL.SFTRST bit to 1.
- Set the SPInCTL.MODEN bit to 1.
5. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the SPInINTF register.
- Set the interrupt enable bits in the SPInINTE register to 1. * (Enable interrupts)
* The initial value of the SPInINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the
SPInINTE.TBEIE bit is set to 1.

12.5.2 Data Transmission in Master Mode

A data sending procedure and operations in master mode are shown below. Figures 12.5.2.1 and 12.5.2.2 show a
timing chart and a flowchart, respectively.
Data sending procedure
1. Assert the slave select signal by controlling the general-purpose output port (if necessary).
2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty).
3. Write transmit data to the SPInTXD register.
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
1 2 3
Dw7 Dw6 Dw5
Dr7 Dr6 Dr5
Dw0 Dw1 Dw2
Dr0 Dr1 Dr2
Seiko Epson Corporation
12 SYNCHRONOUS SERIAL INTERFACE (SPIA)
4 5 6
Dw4 Dw3 Dw2
Dr4 Dr3 Dr2
Dw3 Dw4 Dw5
Dr3 Dr4 Dr5
Loading Dr[7:0] to the SPInRXD register
(Enable input pin pull-up/down)
(Select master mode operating clock)
(Select MSB first/LSB first)
(Select clock phase)
(Select clock polarity)
(Select master/slave mode)
(Execute software reset)
(Enable SPIA Ch.n operations)
(Clear interrupt flags)
7 8
Dw1 Dw0
Dr1 Dr0
Dw6 Dw7
Dr6 Dr7
12-5