Epson S1C17M01 Technical Manual page 191

16 MR SENSOR CONTROLLER (AMRC)
Bit 14 ECH2TRGROT
Bit 13 ECH1TRGROT
Bit 12 ECH0TRGROT
These bits select the direction of rotation as the count-down trigger source for the event counters Ch.2,
Ch.1, and Ch.0. In the event counters Ch.2 and Ch.0, these bits take effect when the AMRCCTL.
ECH02TRGMOD bit = 0.
1 (R/W): Reverse rotation detection
0 (R/W): Normal rotation detection
Bit 11 ECH02TRGMOD
This bit selects the count-down trigger source for the event counters Ch.2 and Ch.0.
1 (R/W): Comparator Ch.1 change (event counter Ch.2)
Comparator Ch.0 change (event counter Ch.0)
0 (R/W): Rotation detection specified by the AMRCCTL.ECH2TRGROT bit (event counter Ch.2)
Rotation detection specified by the AMRCCTL.ECH0TRGROT bit (event counter Ch.0)
Bit 10 MODEN
This bit enables the AMRC operations.
1 (R/W): Enable AMRC operations (The operating clock is supplied.)
0 (R/W): Disable AMRC operations (The operating clock is stopped.)
Note: If the AMRCCTL.MODEN bit is set to 0 during measurement or when the pulse is being
output, the AMRC operating clock is stopped forcibly and subsequent operations cannot
be guaranteed. To stop measurement or pulse output, write 1 to the AMRCCTL.CTLSTP bit
to stop operations and set the AMRCEVPLS.EVEN bit to 0 before setting the AMRCCTL.
MODEN bit to 0.
Bit 9 CTLSTP
This bit terminates measurement.
1 (W): Terminate measurement
0 (W): Ineffective
1 (R): Terminating
0 (R): Stopped
Writing 1 to this bit also terminates output of a pulse.
Bit 8 CTLST
This bit starts measurement.
1 (W): Start measurement
0 (W): Ineffective
1 (R): Starting
0 (R): During measurement/stopped
Bit 7 Reserved
Bit 6 RSTUPCNT
This bit resets the reverse/stop, normal rotation, and unit counters.
1 (W): Reset
0 (W): Ineffective
1 (R): Resetting
0 (R): Reset finished/in normal operations
Bit 5 REVSTPTRG
This bit selects the count source for the reverse/stop counter.
1 (R/W): Reverse rotation detected
0 (R/W): Stop detected
16-10
Seiko Epson Corporation
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)