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Once the SVDINTF.SVDIF bit is set, it will not be cleared even if the power supply voltage subsequently returns
to a value exceeding the SVD detection voltage V
voltage drop, check the power supply voltage status by reading the SVDINTF.SVDDT bit in the interrupt handler
routine.
9.5.2 SVD Reset
Setting the SVDCTL.SVDRE[3:0] bits to 0xa allows use of the SVD reset issuance function.
The reset issuing timing is the same as that of the SVDINTF.SVDIF bit being set when a low voltage is detected.
After a reset has been issued, SVD enters continuous operation mode even if it was operating in intermittent opera-
tion mode, and continues operating. Issuing an SVD reset initializes the port assignment. However, when EXSVD
is being detected, the input of the port for the EXSVD pin is sent to SVD so that SVD will continue the EXSVD
detection operation.
If the power supply voltage reverts to the normal level, the SVDINTF.SVDDT bit goes 0 and the reset state is can-
celed. After that, SVD resumes operating in the operation mode set previously via the initialization routine.
During reset state, the SVD control bits are set as shown in Table 9.5.2.1.
Control register
SVDCLK
SVDCTL
SVDINTF
SVDINTE
9.6 Control Registers
SVD Clock Control Register
Register name
Bit
SVDCLK
15–9 –
8
7
6–4 CLKDIV[2:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8
DBRUN
This bit sets whether the SVD operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bit 7
Reserved
Bits 6–4
CLKDIV[2:0]
These bits select the division ratio of the SVD operating clock.
Bits 3–2
Reserved
Bits 1–0
CLKSRC[1:0]
These bits select the clock source of SVD.
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
SVD
Table 9.5.2.1 SVD Control Bits During Reset State
Control bit
DBRUN
Reset to the initial values.
CLKDIV[2:0]
CLKSRC[1:0]
VDSEL
The set value is retained.
SVDSC[1:0]
Cleared to 0. (The set value becomes invalid as SVD en-
ters continuous operation mode.)
SVDC[4:0]
The set value is retained.
SVDRE[3:0]
The set value (0xa) is retained.
SVDMD[1:0]
Cleared to 0 to set continuous operation mode.
MODEN
The set value (1) is retained.
SVDIF
The status (1) before being reset is retained.
SVDIE
Cleared to 0.
Bit name
Initial
0x00
DBRUN
1
–
0
0x0
0x0
0x0
Seiko Epson Corporation
9 SUPPLY VOLTAGE DETECTOR (SVD)
. An interrupt may occur due to a temporary power supply
Setting
Reset
R/W
–
R
–
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
Remarks
9-5
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