Control Registers; Spia Ch.n Mode Register - Epson S1C17M01 Technical Manual

Master mode
SPInMOD register
CPOL bit CPHA bit
1
0
SPInINTF.TENDIF
Slave mode
SPInMOD register
CPOL bit CPHA bit
1 1
0 0
SPInINTF.TENDIF
Figure 12.6.1 SPInINTF.BSY and SPInINTF.TENDIF Bit Set Timings (when SPInMOD.CHLN[3:0] bits = 0x7)

12.7 Control Registers

SPIA Ch.n Mode Register

Register name Bit
SPInMOD 15–12 –
11–8 CHLN[3:0]
7–6 –
5
4
3
2
1
0
Bits 15–12 Reserved
Bits 11–8 CHLN[3:0]
These bits set the bit length of transfer data.
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
1
SPICLKn
0
SDOn
SPInINTF.BSY
Writing data to the SPInTXD register
#SPISSn
SPInINTF.BSY
SPICLKn
SDOn
SPICLKn
SDOn
Writing data to the SPInTXD register
Bit name Initial
0x0
0x7
0x0
PUEN
NOCLKDIV
LSBFST
CPHA
CPOL
MST
Seiko Epson Corporation
12 SYNCHRONOUS SERIAL INTERFACE (SPIA)
1 2 3
1 2 3
Reset R/W
– R –
H0 R/W
– R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
7 8
7 8
Remarks
12-11